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研究生： 蔡正雄
Tsai, Cheng-Hsiung
論文名稱： 單晶片系統之時脈分佈網路
Clock Distribution Network for SoC
指導教授： 賴源泰
Lai, Yen-Tai
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2003
畢業學年度： 91
語文別： 英文
論文頁數： 48
中文關鍵詞： 單晶片系統 、時脈參差不齊 、時脈分佈網路
外文關鍵詞： clock distribution network, SoC, clock skew
相關次數： 點閱：106  下載：2 
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    • 隨著製程演進至深次微米（deep sub-micro），整個系統以單一晶片來實現（system-on-a-chip, SoC）將是未來晶片設計的趨勢。但在進入深次微米後，於實體電路中產生許多寄生效應，如：導線所造成的延遲（wire delay）問題等，越來越嚴重，已不能忽略。此時實體電路自動化設計（physical design automation）必須具備處理電路寄生效應的能力，以及龐大的電晶體數目的效能。
    本論文中，我們提出一個新的彈性時脈分佈網路設計，不僅可以評估並處理時脈參差不齊(clock skew)問題，同時經由調整“彈性電容”(flexible capacitance)的值，即可支援單晶片系統“即插即用”(plug-and-play)的概念，因此能夠整合整個單晶片系統運作並提升設計效能，減少回頭改進（iterative improvement）以減少設計成本。

    As fabrication technology gets into deep sub-micro era, System-on-a-Chip (SoC) becomes an essential trend for high performance circuit design. However, physical design automation is getting more and more complex due to parasitic effects, e.g. wire delay, etc. In this situation, the design methodology has to face a new challenge to resolve the issues of SoC.
    In this paper, we propose a new flexible clock distribution network design to solve the clock skew problem and support “plug-and-play” in SoC integrated overall SoC operation. Reduce the design cost due to iterative improvement in the integrated design.

    ABSTRACT CONTENTS LIST OF TABLES LIST OF FIGURES Chapter 1 Introduction…………………………………………1 1.1 System-On-a-Chip………………………………………………1 1.2 SoC Integration Methodology.………………………………2 1.2.1 Core-Based………………………………………………………3 1.2.2 Platform-Based…..……………………………………………3 1.2.3 Synthesis-Based…….…………………………………………4 1.3 Deep Sub-Micron Issues…..…………………………………4 1.4 VLSI Design Flow....…………………………………………6 1.5 Physical Design Automation…………………………………6 1.6 Motivations………...…………………………………………9 Chapter 2 Clock Skew Issues……………..…………………11 2.1 Clock Characteristics………………………………………11 2.2 Wire Delay and Clock Skew…………………………………12 2.3 Wire Delay vs. Logic Delay...……………………………13 2.4 Clock Frequency.…………...………………………………14 2.5 Clock Skew.…………………..………………………………17 2.5.1 Positive Clock Skew. ………..……………………………17 2.5.2 Negative Clock Skew….…………………………………….19 Chapter 3 Methods for Clock Routing Problem………..…21 3.1 Clock Routing Problem………………………………………21 3.2 Clock Tree Generation Classification.………………..22 3.3 Clock Tree Structure..….…………………………………23 3.4 Geometry Balanced Clock Routing…………………………23 3.5 Capacitance Delay Balanced Clock Routing..………….26 3.6 Minimum Wire Length...…………………………………….28 Chapter 4 Flexible Clock Distribution Network..………31 4.1 New Concept……………………………………………...….31 4.2 Preliminary………………………....………………………33 4.3 Bottom-Up Phase...………………………………………...35 4.3.1 Routing Topology.…….…….………………………………35 4.3.2 Merging Region Construction….………………………….36 4.3.3 Notations and Definitions..….………………………….36 4.4 Top-Down Phase....………………………………………….38 4.5 Illustration for Two-Phase Process….....……………38 4.6 Complexity Analysis…………….….....…………………41 Chapter 5 Experimental Results and Conclusions……….42 5.1 Experimental Results…………………..………………….42 5.2 Conclusions………..…………….….....…………………44 REFERENCES……………………...………………………………………46

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