針對RISC CPU執行時的效能之改進與降低功率消耗，本論文提出利用新的指令快取記憶體機制並配合內嵌於CPU 指令遞送級的支援電路讓指令的使用得到更佳的效果，並對整個系統架構作性能分析。
本架構採用ARM處理器為基礎的RISC CPU，配合低功率指令遞送機制的歷程快取記憶體(Trace Reuse cache)的小幅度修改，讓處理器能夠在不增加過多面積的情況下支援本架構所採用的處理器指令運送機制，達到降低指令快取記憶體的能源耗用率，並盡可能提昇執行效能的目標。整體的架構將透過EDA設計工具來測得效能改善率，並與原始架構作比較並分析優劣，取得較為準確的實驗數據。
根據實驗結果，使用歷程快取記憶體搭配傳統指令快取記憶體的系統相較於一般只使用傳統指令快取記憶體的系統，能夠達到更好的表現效能，並且為降低整個系統的能源耗用率方面做出進一步的貢獻。除了提供設計者能夠有更多選項外，也讓整體系統的功能性有提昇的空間。

In this thesis, we propose a new mechanism named Trace Reuse Cache (TRC) for instructions delivery to reduce power consumption of RISC processor architecture. With additional circuit in CPU fetch stage and TRC, it is possible to choose suitable instructions in the system for reuse, and to get better performance. We also analyze the whole system and evaluate the IPC, hit rate, and power consumption.
Based on an ARM-compatible 5-stage RISC core, we attach the TRC to the cache memory system and modify part of the pipeline architecture for supporting TRC instruction delivery with small area overhead. The purpose is to lower the power consumption of cache itself and benefit the instruction fetching performance.
Experimental result shows that there is less power dissipation in our work than traditional case only with an instruction cache. Moreover, TRC provides the designer with an additional option, and has possibility to enhance system.

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