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研究生: 李俊逸
Li, Jun-Yi
論文名稱: 前瞻式酷迪客
Sign lookahead CORDIC
指導教授: 賴源泰
Lai, Yen-Tai
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2008
畢業學年度: 96
語文別: 英文
論文頁數: 52
中文關鍵詞: 酷迪客前瞻式
外文關鍵詞: CORDIC, Lookahead
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  • 在電腦處理向量旋轉時,CORDIC 是一個廣為人知的迭代式演算法。它較慢的迭
    代速度是一個很大的缺點。我們使用了一些技巧來減少它旋轉(迭代)次數,我們的靈
    感來自於前瞻式進位加法器(CLA)。
    在這篇論文裡我們提出了快速的演算法與架構。因為我們可以預測旋轉方
    向,使得這個架構可以一併處理多次旋轉,因而大大的提升了運算的速度。

    The CORDIC algorithm is a well-known iterative method for the computation of vector
    rotation. However, the major disadvantage is its relatively slow computational speed. We
    use some techniques inspired by CLA (carry lookahead adder) to reduce the times of
    rotation.
    In this thesis, we present a fast algorithm and architecture for CORDIC. We can predict
    the direction of next several rotations. This can process multiple iterations within one
    rotation. This greatly improves the processing rate.

    CONTENTS ABSTRACT CONTENTS LIST OF FIGURES LIST OF TABLES Chapter 1 Introduction.................................................................... 1 1.1 Motivation....................................................................................... 1 1.2 Thesis Organization ........................................................................ 2 Chapter 2 Previous Work ............................................................... 3 2.1 Carry Lookahead Adder.................................................................. 3 2.1.1 Unrolling The Carry Recurrence .......................................... 4 2.1.2 Carry-Lookahead Adder Design........................................... 6 2.2 Carry Save Adder............................................................................ 9 2.2.1 Redundant Number System..................................................10 2.2.2 Carry-Save Adder Design.....................................................16 Chapter 3 The CORDIC Algorithms........................................21 3.1 Introduction.....................................................................................21 3.2 Rotations And Pseudorotations.......................................................21 3.3 Basic CORDIC Iterations ...............................................................24 3.4 CORDIC Hardware ........................................................................27 Chapter 4 Sign lookahead CORDIC Architecture..............29 4.1 Iterations..........................................................................................30 4.2 Sign Prediction ................................................................................35 4.3 Parallel Shift and Vertical Shift.......................................................37 4.3.1 P-circuit................................................................................37 4.3.2 V-circuit ...............................................................................39 4.3.3 Canceling Method................................................................40 4.4 Hardware .........................................................................................44 Chapter 5 Comparison and Conclusion .................................45 5.1 Expansion ........................................................................................45 5.2 Execution Time................................................................................48 5.3 Comparison .....................................................................................49 REFERENCES.......................................................................................51

    REFERENCES
    [1] Avizienis, A., “Signed-Digit Number Representation for Fast Parallel
    Arithmetic,” IRE Trans. Electronic Computers, Vol. 10, pp.389-400,
    1961.
    [2] C.-S. Wu, A. –Y. Wu, “Modified vector rotational CORDIC
    (MVR-CORDIC) algorithm and architecture,” Circuits and Systems II:
    Analog and Digital Signal Processing, IEEE Transactions on Vol. 48,
    Issue 6, pp. 548 – 561, 2001
    [3] Dawid, H.; Meyr, H, “VLSI implementation of the CORDIC algorithm
    using redundant arithmetic,” Circuits and Systems, 1992. ISCAS '92.
    Proceedings., 1992 IEEE International Symposium on Vol. 3, pp. 1089 –
    1092, 1992.
    [4] Doran, R. W., “Variants of an Improved Carry Look-Ahead Adder,”
    IEEE Trans. Computers, Vol. 37, No. 9, pp. 1110-1113, 1988.
    [5] E. F. Deprettere, P. Dewilde, and R. Udo, “Pipelined CORDIC I
    architectures for fast VLSI filtering,” in Proc. IEEE Int. Con8 on ASSP,
    pp. 1-4, 1984.
    [6] J. E. Volder, “The CORDIC trigonometric computing technique,” IRE
    Trans. Electronic Computing, vol. EC-8, pp. 330-34, September 1959.
    [7] Kantabutra, V., “A Recursive Carry-Lookahead/Carry-Select Hybrid,”
    IEEE Trans. Computers, Vol. 42, No. 12, pp. 1495-1499, 1993.
    [8] Kornerup, P., “Digit-Set Conversions: Generalizations and Applications,”
    IEEE Trans. Computers, Vol. 43, No. 8, pp. 622-629, 1994.
    [9] Lynch, T., and E. Swartzlander, “A Spanning Tree Carry Lookahead
    Adder,” IEEE Trans. Computers, Vol. 41, No. 8, pp. 931-939, 1992.
    [10] Metze, G., and J.E. Robertson, “Elimination of Carry Propagation in
    52
    Digital Computers,” Information Processing ’59 (Proceedings of a
    UNESCO Conference), 1960, pp. 389-396.
    [11] Parhami, B., and S. Johansson, “A Number Representation Scheme with
    Carry-Free Rounding for Floating-Point Signal Processing Applications,”
    Proc. Int’l. Conf. Signal and Image Processing, Las Vegas, Nevada,
    October 1998, pp. 90-92.
    [12] Parhami, B., ”Carry-Free Addition of Recoded Binary Signed-Digit
    Numbers,’’ IEEE Trans. Computers, Vol. 37, No. 11, pp. 1470-1476,
    1988.
    [13] Parhami, B., “Generalized Signed-Digit Number Systems: A Unifying
    Framework for Redundant Number Representations,” IEEE Trans.
    Computers, Vol. 39, No. 1, pp. 89-98, 1990.
    [14] Parhami, B., “On the Implementation of Arithmetic Support Functions
    for Generalized Signed-Digit Number Systems,” IEEE Trans. Computers,
    Vol. 42, No. 3, pp. 379-384, 1993.
    [15] Phatak, D. S., and I. Koren, “Hybrid Signed-Digit Number Systems: A
    Unified Framework for Redundant Number Representations with
    Bounded Carry Propagation Chains,” IEEE Trans. Computer, Vol.43, No.
    8, pp. 880-891, 1994.
    [16] Sugla, B., and D. A. Carlson, “Extreme Area-Time Tradeoffs in VLSI,”
    IEEE Trans. Computers, Vol. 39, No. 2, pp. 251-257, 1990.
    [17] Y. H. Hu, “CORDIC-based VLSI architectures for digital signal
    processing,” IEEE Signal Processing Magazine, pp. 16-35, July 1992.

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