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研究生: 詹朝景
Chan, Chao-Ching
論文名稱: 逆摻雜製程對高壓金氧半電晶體特性與可靠度影響之研究
Effects of Counter-Doping Process on the Characteristics and Reliability of High Voltage MOS Transistors
指導教授: 陳志方
Chen, Jone-Fang
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 微電子工程研究所
Institute of Microelectronics
論文出版年: 2018
畢業學年度: 106
語文別: 英文
論文頁數: 74
中文關鍵詞: 高壓金氧半場效電晶體輕摻雜汲極熱載子導致之退化電腦輔助設計模擬
外文關鍵詞: HVMOSFET, LDD, hot-carrier-induced degradation, TCAD simulation
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  • 在本論文中, 我們所使用的元件為N型空乏式高壓金氧半場效電晶體(HV-MOSFET),並且在輕摻雜區(Lightly Doped Drain)使用不同的逆摻雜(counter-doping)製程,此高壓元件應用於NAND Flash之周邊控制電路中,由於元件會操作在高電壓的環境,因此熱載子可靠度為相當重要的議題,我們將探討不同汲極逆摻雜製程及操作偏壓狀態對於元件電特性與熱載子可靠度的影響,並藉由電腦輔助設計(TCAD)模擬軟體來協助進行實驗數據的分析。
    本篇第一個部分是研究逆摻雜製程中佈植的BF2濃度及能量造成的影響,雖然增加BF2濃度有助於改善元件之崩潰電壓,但伴隨而來沿著輕摻雜區表面延伸的撞擊離子化效應(impact ionization)與更貼近表面的電流路徑都導致更嚴重的電流退化現象。另一方面,從實驗數據中無法明顯地觀察到不同BF2佈植能量對電特性及可靠的的影響,無論是撞擊離子化效應的分布或是電流的深淺在模擬結果中都呈現出可以忽略的差異,因此我們認為調整佈植能量在此特定濃度的情況中無法有效的改善元件的特性。
    在第二個部分討論的是不同操作狀態下退化機制的轉變,我們得知元件在啟動狀態(on-state)時會隨著時間呈現劇烈的電流退化,其原因來自輕摻雜區中較嚴重的撞擊離子化效應,然而在次臨界狀態(subthreshold-state)中,元件雖然呈現較平緩的退化斜率,但在實驗初期就出現嚴重的退化,這是因為較低的閘極偏壓會增強閘極側壁(spacer)區的電場,導致更加嚴重的熱電洞住入(hot-hole injection)現象,此結果顯示即使元件操作在通道尚未形成的狀態,熱載子效應的影響依然是需要注意的問題。

    In this thesis, the devices we studied are N-type depletion-mode high voltage MOSFETs (HV-MOSFETs) fabricated with various counter-doping processes in lightly doped drain region. Because the HV device is applied in periphery circuit of NAND Flash Cell to endure high voltage from power supply, the hot-carrier reliability is one of the most important issues to be considered. Therefore, the influence of counter-doping processes and operating states on hot-carrier reliability was investigated. Also, the technology computer-aided design (TCAD) simulation was utilized to analyze the experiment data.
    First, we discussed the effect of BF2 implant dose and energy. Although higher breakdown voltage can be obtained by increasing the BF2 dose, the extension of impact ionization and the shallower current path lead to more serious degradation. On the other hand, when the implant energy is increased, there is no obvious change of hot-carrier degradation can be observed. The simulation results present that both I-I rate and current path have negligible difference. As a result, we considered that adjusting implant energy in our dose condition is not an effective method to optimize device behavior.
    Next, the transformation of degradation mechanism in various stress voltages was investigated. Because serious impact ionization takes place in LDD region, the device after on-state stress shows the most serious Idlin degradation. In subthreshold condition, the enhance in maximum electric field also leads to large Idlin degradation in beginning period of stress. It indicates that this hot-carrier effect in low gate operating voltage is necessary to be concerned.

    中文摘要 I Abstract III 致謝 V Content VI Table Captions VIII Figure Captions IX Chapter 1 1 1-1 Motivation of the Thesis 1 1-2 Introduction of High Voltage MOS transistors 3 1-3 Introduction of Hot Carrier reliability 4 1-4 About the thesis 5 Chapter 2 10 2-1 Introduction 10 2-2 Device structure description 10 2-3 Measurement Methodology 11 2-3-1 Measurement setup 11 2-3-2 ID-VG measurement 11 2-3-3 VBD measurement 12 2-3-4 ISUB-VG measurement 13 2-3-5 The discussion of characteristic 13 2-4 Summary 15 Chapter 3 27 3-1 Introduction 27 3-2 Experiment setup and stress condition 27 3-3 Experiment results and discussion 28 3-4 The effect of BF2 dose and energy on degradation 29 3-5 Summary 33 Chapter 4 50 4-1 Introduction 50 4-2 Experiment setup and stress condition 50 4-3 Experiment results and discussion 51 4-4 Summary 54 Chapter 5 64 5-1 Conclusion 64 5-2 Future Work 65 Reference 66

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