邏輯非揮發性記憶體有著能跟邏輯製程進行整合的特點，因此在需要嵌入記憶體的電路中時常被使用到。不過由與本身的結構設計，自身的面積會較為龐大，使得儲存空間小於外插式記憶體許多。
本論文根據現在新式的製程環繞式閘級製程結構設計了邏輯非揮發性記憶體。如此一來不僅能縮小面積，並且能了解跟新式製程之間的相容性。那在設計出結構後，我們利用TCAD模擬元件進行編程和擦除的動作，其中考慮到穿隧機制以及熱載子機制。在初步的模擬後，藉由調整結構的參數，進行記憶體儲存能力的優化，使得記憶窗大幅增加。在優化的過程，了解元件要改善所需要調整的方向。
在完成元件的改良後，研究的下一步為設計出元件之間的接線方式以組成記憶體陣列，包括NAND跟NOR型態的陣列。在組成記憶體陣列後，我們成功的模擬出記憶體陣列中元件之間的互動。證實了邏輯非揮發性記憶體跟環繞式閘級製程之間的匹配度。

Logical non-volatile memory is often used in circuits requiring embedded memory because it can be integrated with logic processes. However, its area is larger due to its structural design, making the storage space much smaller than the external memory.
This study designed a logical non-volatile memory based on a state-of-the-art gate-all-around (nanosheet) process. In this way, we not only reduce the area but also investigate the compatibility with the new process. Then, after designing the structure, we use TCAD to simulate the device for programming and erasing operations, considering the tunneling and hot carrier mechanisms. After finishing the initial simulation, the memory storage capacity is optimized by adjusting the parameters of the structure, resulting in a significant increase in the memory window. During the optimization process, the directions that need to be adjusted to improve the components are understood.
After improving the components, the next step of the study is to design the interconnections between the components to form memory arrays, including NAND and NOR type arrays. After building the memory arrays, we successfully simulated the circuitry between the components in the memory arrays. The compatibility between the logical non-volatile memory and the GAA process is confirmed.

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