本論文為研究振盪電路並追求高準確度的訊號設計。提出一個融合兩獨特架構的電路設計，推導相關公式並用以優化設計使其具備高度的信號準確率。採用互補式電晶體架構，並利用相關理論輔助設計，使其優化後的電路能夠產生更高準確性的四相位訊號。佈局時利用國家晶片系統設計中心的規則佈置接點(Pad)的位置，並委託該單位進行探針量測。量測結果為在離中心頻率1 MHz處之相位雜訊為-121 dBc/Hz，功耗在1.8伏供應電壓時為3.81毫瓦，此時正交相位誤差小於0.1度而正交振幅誤差0.006 dB。考慮四個相位訊號時，相位誤差為0.58度，而振幅誤差為0.448dB。第二版本的晶片採用TSMC 0.18μm 1P6M CMOS製程實現，並委託國家晶片系統設計中心量測。

This paper proposes a quadrature voltage-controlled oscillator (QVCO) using capacitive source degeneration coupling (CSDC) and spontaneous transconductance matching (STM) techniques. Because the mismatch in QVCO structure will result in serious phase error and gain error, a CSDC structure is used to overcome phase error and a STM structure is adopted to reduce the gain error, respectively. Moreover, in order to design a remarkable phase error of less than 0.1°, a systematic analysis of QVCO on the proposed techniques is presented. The measurement results reveal the proposed QVCO has the phase error less than 0.07o at 2.45 GHz. The measured phase noise is -121 dBc/Hz at 1-MHz offset while consumes 3.81 mW under a 1.8-V supply voltage to achieve the figure of merit of -182.98. The tuning range is between 2.303 and 2.475 GHz to fit the requirement of IEEE 802.15.4.

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