多重模式里德－所羅門解碼器是一種具有多種不同改錯能力的設計。它提供了一種富彈性的共同解決方案,以因應系統在不同通道環境下的需求。在多重模式解碼器中，往往需要使用到所謂的係數選擇器，而此電路包含了大量的多工器，以用來調整解碼器內部模式切換時的資料流。在本論文中，我們所提出之設計主要改良自基於Sarwate所提之reformulated　inversionless　Berlekamp-Massey演算法架構，我們首先利用折疊技巧，使其能在不犧牲資料輸出速率的原則下，依然符合絶大多數的應用。同時，配合我們所發展的無係數擇器之硬體配置方式，可使本設計不僅具有低成本的優點，更能因其架構簡單且有高度的規則性而利於VLSI的實現。
　　經由UMC　0.18um　1P6M的製程實作後發現,本設計之解碼器的最快操作時脈為400MHz，資料處理速率則可達到3.2Gbps。相對於目前其他基於extended　Euclidean演算法的設計而言，本解碼器兼具有面積上與效能上的優勢。綜合上述所言，本論文所提出之架構可適用於大部分一般性的應用。

　Multi-mode Reed-Solomon (RS) decoders provide a flexible and possibly unified solution that can be used in systems demanding various levels of error-immunity capability for economically handling different channel conditions. Inside the multi-mode RS decoders, circuitry composed of a large amount of multiplexers, known as the coefficient selector, might be employed to adjust the data flows between processing elements so as to comply with different operation modes. In this thesis, a folded architecture of RS decoders is first derived based on the reformulated inversionless Berlekamp-Massy architecture derived by Sarwate, which can retain the throughput rate of the reformulated architecture in many practical applications. In conjunction with the developed coefficient-selector-free multi-mode arrangement, the resulting design possesses not only area-efficient property but also very simple and regular interconnect topology that makes it very suitable for VLSI realization.
　Implementation results exhibit that the achievable throughput rate of the developed decoder, implemented in UMC 0.18um 1P6M process, is 3.2Gbps at the maximum clock rate of 400MHz. It provides both area and speed advantages in comparison with the existing work based on extended Euclidean algorithm. In summary, the proposed high-performance architecture can be applied to most practical applications.

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