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研究生： 黃意婷
Huang, Yi-ting
論文名稱： 一個六位元二億二千萬取樣頻率連續逼近式類比數位轉換器
A 6-bit 220-MS/s Successive-Approximation Analog-to-Digital Converter
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 80
中文關鍵詞： 類比數位轉換器
外文關鍵詞： asynchronous processing, time interleaved, SAR ADC
相關次數： 點閱：142  下載：11 
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    • 於本論文中，我們實現了一個六位元二億二千萬取樣頻率連續逼近式類比數位轉換器，並使用一個節省開關能源的操作方式來達到低功率消耗。相較於傳統形式，平均電容陣列的開關所需消耗的能源可減少81%。本設計使用台積電 0.18 微米製程下線驗證，其核心電路的面積為0.24 mm  0.13 mm。量測結果顯示在二億二千萬的取樣頻率下，有效位元數為5.13位元，消耗功率為6.8 mW。有效信號頻寬為二億赫茲。每一次資料轉換消耗 0.88 pJ。

    This thesis reports the implementation of a 6-bit 220-MS/s low-power high-speed successive-approximation (SAR) analog-to-digital converter (ADC). A set-and-down switching sequence technique is proposed to reduce the power consumption of the ADC. Compared to the conventional switching method, the average switching energy is reduced by 81%. This proposed ADC is fabricated in TSMC 0.18-m 1P5M digital CMOS process, and only occupies 0.24 mm  0.13 mm active area. Measurement results show that the maximum effective number of bits (ENOB) is 5.13 bits and the power consumption is 6.8 mW at the sampling frequency of 220 MHz. Also, the effective resolution bandwidth (ERBW) is 200 MHz. Accordingly, the figure-of-merit (FOM) is only 0.88 pJ/conversion-step.

    List of Figures x List of Tables xii Chapter 1 Introduction 1 1.1 MOTIVATION 1 1.2 THESIS ORGANIZATION 3 Chapter 2 Analog-to-Digital Converter 4 2.1 INTRODUCTION 4 2.2 ADC PERFORMANCE METRICS 6 2.2.1 Resolution 6 2.2.2 Accuracy 7 2.2.3 Static Specifications 7 2.2.4 Dynamic Specifications 12 2.3 ADC ARCHITECTURES 17 2.3.1 Flash Architecture 18 2.3.2 Two-Step Architecture 19 2.3.3 Pipelined Architecture 21 2.3.4 Algorithmic (or Cyclic) Architecture 23 2.3.5 Successive-Approximation (SAR) Architecture 25 2.4 SUMMARY OF ADC ARCHITECTURES 26 Chapter 3 The Basics of Time-Interleaved and SAR ADC 29 3.1 THE BASIC OF TIME-INTERLEAVED ADC 29 3.2 THE BASIC PRINCIPLE OF SAR ADC 31 3.2.1 The Operation of SAR ADC 31 3.3 ASYNCHRONOUS PROCESSING 38 Chapter 4 Architecture Design 41 4.1 INTRODUCTION 41 4.2 ARCHITECTURE COMPARISON 43 4.3 THE OPERATION OF CAPACITOR SWITCHING METHOD 45 4.4 CHANNEL MATCHING 52 4.5 CIRCUIT IMPLEMENTATION 53 4.5.1 Comparator Description 53 4.5.2 Timing Control and SAR Logic 56 4.5.3 Sampling Network Design 59 4.5.4 Digital-to-Analog Converter 63 4.6 LAYOUT AND MEASUREMENT SETUP 66 4.7 MEASUREMENT RESULT 68 4.8 COMPARISON AND DISCUSSION 72 Chapter 5 Conclusion and Future Work 74 Bibliography 76

    Bibliography

    [1] C.-S. Lin and B.-D. Liu, “A new successive approximation architecture for low-power low-cost CMOS A/D converter,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 54-62, Jan. 2003.
    [2] B. P. Ginsburg and A. P. Chandrakasan, “Dual time-interleaved successive approximation register ADCs for an ultra-wideband receiver,” IEEE J. Solid-State Circuits, vol. 42, no. 2, pp. 247-257, Feb. 2007.
    [3] B. P. Ginsburg and A. P. Chandrakasan, “500-MS/s 5-bit ADC in 65-nm CMOS with split capacitor array DAC,” IEEE J. Solid-State Circuits, vol. 42, no. 4, pp. 739-747, Apr. 2007.
    [4] B. P. Ginsburg and A. P. Chandrakasan, “An energy-efficient charge recycling approach for a SAR converter with capacitive DAC,” in Proc. 1991 Int. Symp. Circuits and Syst., May. 2005, pp. 184-187.
    [5] J. Craninckx and G. Van der Plas, “A 65fJ/conversion-step 0-to-50MS/s 0-to-0.7mW 9b charge-sharing SAR ADC in 90nm digital CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2007, pp. 246-247.
    [6] D. Johns and K. Martin, Analog Integrated Circuit Design. New York: John Wiley&Sons, 1997.
    [7] 蘇逸霈, “An analog-to-digital converter with DLL clock generator,” MS Thesis, National Taiwan Univ., Taiwan, Jul. 2006.
    [8] 張哲維, “Design and application of analog-to-digital converter,” MS Thesis, National Taiwan Univ., Taiwan, Jul. 2007.
    [9] 鄭光偉, “1.0-V 10-bit CMOS pipelined analog-to-digital converters,” MS Thesis, National Taiwan Univ., Taiwan, Jul. 2002.
    [10] M. Waltari and K. Halonen, Circuit Techniques for Low-Voltage and High-Speed A/D Converters. Kluwer Academic Publishers, 2002.
    [11] R. V. D. Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters. Kluwer Academic Publishers, 1994.
    [12] B. Razavi, Principles of Data Converter System Design, New York: John Wiley&Sons, 1995.
    [13] K. Uyttenhove and Michiel S. J. Steyaert, “A 1.8-V 6-Bit 1.3-GHz flash ADC in 0.25-m CMOS,” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1115–1122, July 2003.
    [14] B. S. Song, S. H. Lee, and M. F. Tompsett, “A 10-b 15MHz CMOS recycling two-step A/D converter,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1328–1338, Dec. 1990.
    [15] T. B. Cho and R. Gary, “A 10 b, 20 Msample/s, 35mW pipeline A/D converter,” IEEE J. Solid-State Circuits, vol. 30, no. 3, pp. 166-172, Apr. 1995.
    [16] S. H. Lewis, H. S. Fetterman, G. F. Gross, J. R. Ramachandran, and T. R. Viswanathan, “A 10-b 20-Msample/s analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 27, no. 3, pp. 351–358, Mar. 1992.
    [17] T. Sekino, M. Takeda, K. Koma, “A monolithic 8b two-step parallel ADC without DAC and subtractor circuits,” in ISSCC Dig. Tech. Papers, Feb. 1982, pp. 46-47.
    [18] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, “A ratio-independent algorithmic analog-to-digital conversion technique,” IEEE J. Solid-State Circuits, vol. 19, no. 6, pp. 828-836, Dec. 1984.
    [19] N. Kurosawa, H. Kobayashi, K. Maruyama, H. Sugawara, and K. Kobayashi, “Explicit analysis of channel mismatch effects in time-interleaved ADC systems,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 48, no. 3, pp. 261-271, Mar. 2001.
    [20] Y. Oh and B. Murmann, “System embedded ADC calibration for OFDM receivers,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol. 53, no. 8, pp. 1693-1703, Aug. 2006.
    [21] D. M. Hummels, “Distortion compensation for time-interleaved analog-to-digital converters,” in Proc. IEEE Inst. and Measurement Tech. Conf., Jun. 1996. pp. 728-731.
    [22] G. Geelen, “A 6-b 1.1-Gsample/s CMOS A/D converter,” in ISSCC Dig. Tech. Papers, Feb. 2001, pp. 128-129.
    [23] P. Scholtens and M. Vertregt, “A 6-bit 1.6-GSample/s flash ADC in 0.18-m CMOS using averaging termination,” IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1599-1609, Dec. 2002.
    [24] C. Sandner, M. Clara, A. Santner, T. Hartig, and F. Kuttner, “A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-m digital CMOS,” IEEE J. Solid-State Circuits, vol. 40, no. 7, pp. 1499-1505, Jul. 2005.
    [25] H.-C. Kim, D.-K. Jeng, and W. Kim, “A 30mW 8b 200MS/s pipelined CMOS ADC using a switched-opamp technique,” in ISSCC Dig. Tech. Papers, Feb. 2005, pp. 284-285.
    [26] S. Gupta, M. Choi, M. Inerfield, and J. Wang, “A 1GS/s 11b time-interleaved ADC in 0.13m CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2006, pp. 576-577.
    [27] J. L. Mccreary and P. R. Gray, “All-MOS charge redistribution analog-to-digital conversion techniques-Part I,” IEEE J. Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
    [28] S.-W. M. Chen and R. W. Brodersen, “A 6-bit 600-MS/s 5.3-mW asynchronous ADC in 0.13-m CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669-2680, Dec. 2006.
    [29] Y. Oh and B. Murmann, “A low-power, 6-bit time-interleaved SAR ADC using OFDM pilot tone calibration,” in Proc. IEEE Cust. Int. Circuits Conf., Setp. 2007, pp. 193-196.
    [30] B. P. Ginsburg and A. P. Chandrakasan, “High interleaved 5b 250MS/s ADC with redundant channels in 65nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 240-241.
    [31] K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Montijo, “A 20 GS/s 8 b ADC with a 1MB memory in 0.18m CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2003, pp. 318-496.
    [32] S. K. Gupta, M. A. Inerfield, and J. Wang, “A 1-GS/s 11-bit ADC with 55-dB SNDR, 250-mW power realized by a high bandwidth scalable time-interleaved architecture,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2650-2657, Dec. 2006.
    [33] D. Draxelmayr, “A 6b 600MHz 10mW ADC array in digital 90nm CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 264-527.
    [34] S. Gambini and J. Rabaey, “Low-power successive approximation converter with 0.5-V supply in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2348-2356, Nov. 2007.
    [35] B. P. Ginsburg and A. P. Chandrakasan, “Dual scalable 500MS/s, 5b time-interleaved SAR ADCs for UWB applications,” in Proc. IEEE Cust. Int. Circuits Conf., Setp. 2005, pp. 403-406.
    [36] Y.-K. Chang, C.-S. Wang, and C.-K. Wang, “A 8-bit 500KS/s low power SAR ADC for bio-medical applications,” in Proc. IEEE Asian Solid-State Circuits Conf., Nov. 2007, pp. 228-231.
    [37] G. Promitzer, “12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1MS/s,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1138-1143, Jul. 2001.
    [38] M. D. Scott, B. E. Boser, and K. S. J. Pister, “An ultralow-energy ADC for smart dust” IEEE J. Solid-State Circuits, vol. 38, no. 7, pp. 1123-1129, Jul. 2003.
    [39] Z. Cao, S. Yan, and Y. Li, “A 32mW 1.25GS/s 6b 2b/step SAR ADC in 130nm digital CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2008, pp. 542-543.
    [40] K.-S. Tan, S. Kiriaki, M. de Wit, J. W. Fattaruso, C.-Y. Tsay, W. E. Matthews, and R. K. Hester, “Error correction techniques for high-performance differential A/D converters,” IEEE J. Solid-State Circuits, vol. 25, no. 6, pp. 1318-1327, Dec. 1990.
    [41] S. M. Jamal, “Digital background calibration of time-interleaved analog-to-digital converters,” Ph.D. Thesis, Univ. of California at Davis, Davis, 2001.
    [42] C. H. Diaz, D. D. Tang, and J. Y.-C. Sun, “CMOS technology for MS/RF SoC,” IEEE Trans. Electron Devices, vol. 50, no. 3, pp. 557-566, Mar. 2003.
    [43] D. Aksin, M. Al-Shyoukh, and F. Maloberti, “Switch bootstrapping for precise sampling beyond supply voltage,” IEEE J. Solid-State Circuits, vol. 41, no. 8, pp. 1938-1943, Aug. 2006.
    [44] A. M. Abo and P. R. Gray, “A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter,” IEEE J. Solid-State Circuits, vol. 34, no. 5, pp. 599-606, May. 1999.
    [45] S. Jiang, M. A. Do, K. S. Yeo, and W. M. Lim, “An 8-bit 200-MSample/s pipelined ADC with mixed-mode front-end S/H circuit,” IEEE Trans. Circuits Syst. I, Reg. Papers., vol. 53, no. 8, pp. 1693-1703, Aug. 2006.
    [46] S. M. Louwsma, A. J. M. van Tuijl, M. Vertregt, and B. Nauta, “A 1.35 GS/s, 10 b, 175 mW time-interleaved AD converter in 0.13 m CMOS,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 778-786, Apr. 2008.
    [47] K. Cornelissens and M. Steyaert, “A novel bootstrapped switch design, applied in a 400MHz clocked  ADC,” in Proc. IEEE Int. Electronics, Circuits and Systems, Conf., Dec. 2006, pp. 1156-1159.
    [48] W. Black and D. Hodges, “Time interleaved converter arrays,” IEEE J. Solid-State Circuits, vol. SC-15, no. 6, pp. 1022-1029, Dec. 1980.
    [49] M. Seo, M. J. W. Rodwell, and U. Madhow, “Comprehensive digital correction of mismatch errors for a 400-Msamples/s 80-dB SFDR time-interleaved analog-to-digital converter,” IEEE Trans. Microw. Theory Tech., vol. 53, no. 3, pp. 1072-1082, Mar. 2005.
    [50] Z.-M. Lee, C.-Y. Wang and J.-T. Wu, “A CMOS 15-bit 125-MS/s time-interleaved ADC with digital background calibration,” IEEE J. Solid-State Circuits, vol. 42, no. 10, pp. 2149-2160, Oct. 2007.
    [51] D. Dalton, G. Spalding, H. Reyhani, T. Murphy, K. Deevy, M. Walsh and P. Griffin, “A 200-MSPS 6-bit flash ADC in 0.6-m CMOS,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 45, no. 11, pp. 1433-1444, Nov. 1998.
    [52] X. Jiang and M.-C. F. Chang, “A 1-GHz signal bandwidth 6-bit CMOS ADC with power-efficient averaging,” IEEE J. Solid-State Circuits, vol. 40, no. 2, pp. 532-535, Feb. 2005.
    [53] S. Limotyrakis, S. D. Kulchycki, D. Su, and B. A. Wooley, “A 150MS/s 8 b 71 mW time-interleaved ADC in 0.18 m CMOS,” in ISSCC Dig. Tech. Papers, Feb. 2004, pp. 258-259.

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