簡易檢索 / 詳目顯示

回結果列表
研究生： 張宏宇
Chang, Hung-Yu
論文名稱： 針對H.264/AVC動態預測之超大型積體電路架構
A VLSI Architecture For H.264/AVC Motion Estimation
指導教授： 賴源泰
Lai, Yen-Tai
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2012
畢業學年度： 100
語文別： 英文
論文頁數： 101
中文關鍵詞： 移動估測 、H.264/AVC 、超大型積體電路設計
外文關鍵詞： Motion Estimation, H.264/AVC, VLSI design
相關次數： 點閱：65  下載：0 
分享至:
查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報

    • H.264/AVC 是目前最新的視訊編碼標準，比起之前的編碼來有較優的編碼效能。在H.264/AVC中，移動估測(motion estimation, ME)是去除連續幅間的時域冗餘最重要的部分，且也占了H.264/AVC 中高達90%的編碼時間。在H.264/AVC中, 移動估測可以分成兩個部分整數動態預測(integer motion estimation,IME) 跟分數動態預測(fractional motion estimation,FME)。整數動態預測找出整數的動態向量(integer motion vector,IMV)然後分數動態預測在將最佳整數的動態向量提申他的精確度到1/2 或1/4像素。
    本論文中將提出一個H.264/AVC移動估測之超大型積體電路架構。這個架構可分成兩部分,整數動態預測部分與分數動態預測部分,我們提出了一個新的演算法(MFS),這個演算法在搜尋速度及預測精確度中做一個權衡,此外在分數動態預測部分我們也針對內插公式做了改變使得其電路面積降低。
    最後使用Verilog硬體描述語言來實現其電路架構, 再透過Synopsys的Design Compiler與TSMC 0.18㎛製程作電路合成, 實驗結果顯示,跟以往的設計比起來我們的架構可以獲得較少的面積。

    H.264/AVC which is the latest video coding standard, with better encoding performance when comparing with previous coding standard. Motion Estimation(ME) is the most important in H.264/AVC in reducing the temporal redundancy between successive frames and it also takes about 90% of the total encoding time in H.264/AVC. In H.264/AVC, ME can be divided into two parts Integer Motion Estimation (IME) and Fractional Motion Estimation (FME). IME finds the best Integer Motion Vector (IMV) then FME try to refine IMV into half pixel or quarter pixel accuracy.
    In this thesis, a VLSI architecture for H.264/AVC motion estimation is proposed. This architecture can be divided into two parts, IME and FME. In IME, we propose a new algorithm Modify Full Search (MFS) to make a trade off between searching speed and prediction accuracy, while in FME we also make a slight change in its interpolation formula in order to reduce its circuit area.
    In the end, we implement our architecture by Verilog hardware description language, and synthesize the digital circuit by using Design Compiler of Synopsys with the TSMC 0.18㎛CMOS technology. The experimental results show that our architecture can obtain less circuit area than previous design.

    Table of Contents Abstract Table of Content List of Figures List of Tables Chapter1 Introduction 1 1.1 Research Motivation 1 1.2 Thesis Organization 2 Chapter 2 Background 3 2.1 H.264 Overview 3 2.2 Motion Estimation 16 2.3 Motion Compensation 17 2.4 Variable Block Size 18 2.5 Block-Matching Algorithm 18 2.5.1 IME searching Algorithms 19 2.5.2 FME searching Algorithms 25 2.6 Proposed IME Algorithms 30 Chapter 3 Related works 32 3.1 Hardware implementation of video coding standard 32 3.1.1 Hardware architecture in IME 32 3.1.2 Hardware architecture in FME 36 Chapter 4 Propose H.264/AVC Motion Estimation Hardware 45 4.1 Integer Motion Estimation (IME) architecture 48 4.1.1 The architecture of PEarray in IME 48 4.1.2 Processing Element in IME 49 4.1.3 Comparator in IME 50 4.1.4 Memory in IME 52 4.1.5Address generator in IME 53 4.2 Fractional Motion Estimation (FME) architecture 59 4.2.1 The architecture of PEarray in FME 59 4.2.2 Interpolation Unit 60 4.2.3 Memory in FME 61 4.2.4 Processing Element 61 4.2.5 Processing Data Flow 63 4.2.6 Comparator 65 4.2.7 Final address generator 66 Chapter 5 Experimental Results 67 5.1 Synthesis Results 67 5.2 Comparisons 96 Chapter 6 Conclusion 98 References 99 LIST OF TABLES Table 5.1 Comparisons in IME 96 Table 5.2 Comparisons in FME 97 Table 5.3 Comparisons in ME 97 LIST OF FIGURES Fig.2.1 The Encoder Architecture of H.264/AVC 4 Fig.2.2 (a) 4x4 luminance (a to p) with its neighboring pixels (A to L and M) (b) eight 4×4 prediction modes and DC mode 6 Fig.2.3 Intra 4×4 Vertical Mode 7 Fig.2.4 Intra 4×4 Horizontal Mode 7 Fig.2.5 Intra 4×4 DC Mode 7 Fig.2.6 Intra 4×4 Diagonal Down-LeftMode 8 Fig.2.7 Intra 4×4 Diagonal Down-Right Mode 8 Fig.2.8 Intra 4×4 Vertical Right Mode 8 Fig.2.9 Intra 4×4 Horizontal Down Mode 9 Fig.2.10 Intra 4×4 Vertical Left Mode 9 Fig.2.11 Intra 4×4 Horizontal Up Mode 10 Fig.2.12 Slice and slice group 12 Fig.2.13 (a)without In-Loop De-Blocking Filter (b) with In-Loop De-Blocking Filter 14 Fig.2.14 H.264 profile in encoding specification 16 Fig.2.15 The ME process in H.264/AVC 16 Fig.2.16 Two successive video frames 17 Fig.2.17 Block mode in H.264/AVC 18 Fig.2.18 Block matching of two adjacent frames 19 Fig.2.19 The searching process of TSS 22 Fig.2.20 Search pattern of Diamond Search 23 Fig.2.21 Search pattern of Cross Search 24 Fig.2.22 relation between integer(I) pixel half-pixel horizontal(H), vertical(V) and diagonal(D) 26 Fig.2.23 the position of quarter pixel 28 Fig.2.24 The process of MFS 31 Fig.3.1 Motion estimation architecture of Jinwook kim and Taegeun Park 33 Fig.3.2 Raster scan sequence Jinwook kim scan sequence 34 Fig.3.3 Total block pattern for H.264/AVC 34 Fig.3.4 The structure of PE in Jinwook kim 35 Fig.3.5 Fractional motion estimation architecture in Marcel M. Corrêa 36 Fig.3.6 The structure of interpolation unit in Marcel M. Corrêa 37 Fig.3.7 SAD Tree (ST) in Marcel M. Corrêa 38 Fig.3.8 The architecture of SAD comparison in Marcel M. Corrêa 39 Fig.3.9 Total FME architecture in G. A. Ruiz 40 Fig.3.10 The architecture of PE in G. A. Ruiz 41 Fig.3.11 The relative position of PE and integer pixel in G. A. Ruiz 42 Fig.3.12 Half interpolation unit in G. A. Ruiz 43 Fig.3.13 Best half-MV unit in G. A. Ruiz 44 Fig.4.1 Total data flow of propose ME architecture 46 Fig.4.2. The architecture of PEarray in IME 48 Fig.4.3 The architecture of processing element(PE) 49 Fig.4.4 The architecture of two-level comparator 51 Fig.4.5 The architecture of final comparator 52 Fig.4.6The memory block partition 53 Fig.4.7 iag 54 Fig.4.8 IME address generator 54 Fig.4.9 The architecture for generating other block size 56 Fig.4.10 Four region in a 8x8 block 56 Fig.4.11 Address transform 57 Fig.4.12 The relationship between one-dimension and two-dimension 57 Fig.4.13 The architecture of PEarray in FME 59 Fig.4.14 The relative position of each PE and best IMV 59 Fig.4.15 The architecture of half pixel interpolation unit 60 Fig.4.16 The PE architecture in FME 62 Fig.4.17 Data flow for each PE 63 Fig.4.18 interpolated half−pixels around the integer pixels 64 Fig.4.19 The architecture of comparator in FME 65 Fig.4.20 The architecture of final address generator 66 Fig.5.1 The architecture of PE in IME 68 Fig.5.2 PE architecture in FME 72 Fig.5.3 synthesis result in IME 76 Fig.5.4 Synthesis result in FME 83 Fig.5.5 The total ME synthesis result 89

    [1] “Draft ITU-T Recommendation and Final Draf International Standard of Joint Video Specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC),” Joint Video Team (JVT) of ISO/IEC MPEG and ITU-T VCEG, JVT-G050, 2003.
    [2] K, M. Yang, M. T. Sun, and L. Wu, “A Family of VLSI Designs for the Motion Compensation Block-Matching Algorithm,” IEEE Trans.on Circuits and Systems,vol. 36, no. 10, pp. 1317-1325, Oct. 1989.
    [3] T. Wiegand, G. J. Sullivan, G. Bjontegaard, and A.Luthra, “Overview of the H.264/ AVC video coding standard,” IEEE Trans. Circuits Syst. Video Technol., vol. 13, no. 7, pp. 560–576, Jul. 2003.
    [4]Jian-Wen Chen, Chao-Yang Kao and Youn-Long Lin. “Introduction to H.264 advanced standard,” in Proc. of IEEE Asia and South Pacfic. Conf.,pp.736-741. Jan. 2006.
    [5] R. Li, B. Zeng, and M. L. Liou, “A New Three-Step search Algorithm for Block Motion Estimation , “ IEEE Trans. on Circuits Systems and Video Technology, vol. 4, pp. 438-442, Aug. 1994.
    [6]Li Zhang and Wen Gao “Reusable Architecture and Complexity-Controllable Algorithm for the Integer/Fractional Motion Estimation of H.264” IEEE Trans. On Consumer Electronics pp. 749-756 May 2007.
    [7]G.A. Ruiz and J.A. Michell, “An Efficient VLSI Architecture for Fractional Motion Estimation in H.264 for HDTV,” Springer. On Journal of Signal Processing Systems pp 443-457 Mar. 2011
    [8] J. Kim and T. Park, “A Novel VLSI Architecture for Full-Search Variable Block-Size Motion Estimation, “ IEEE trans. on Consumer Electronics, vol. 55, pp. 728-733, May 2009.
    [9] Marcel M. Corrêa, Mateus T. Schoenknecht and Luciano V. Agostini, “A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Motion Estimation Refinement,” SBCCI '10 Proceedings of the 23rd symposium on Integrated circuits and system design ACM New York, NY, USA pp151-156 , 2010
    [10] M. Corrêa, M. Schoenknecht, R. Dornelles, L. Agostini, “A High Performance Hardware Architecture for the H.264/AVC Half-Pixel Interpolation Unit”, VI Southern Programmable Logic Conference, March 2010.
    [11] T. C. Chen, Y. W. Huang, and L. G. Chen, “Fully utilized and reusable architecture for fractional motion estimation of H.264/AVC,”in Proc.IEEE Int.Conf.Acoust.,Speech, Signal Process.,May 2004, vol. 4, pp.9–12.
    [12] Y. J. Wang, C.-C. Cheng, and T.-S. Chang, “A fast fractional-pel motion estimation algorithm for H.264/AVC,” in Proc. IEEE Int. Symp.Circuits Syst., May 2006, pp. 3974–3977.
    [13] C. L. Su, W. S. Yang, Y. Li, C. W. Chen, J. I. Guo, and S. Y. Tseng,“Low complexity high quality fractional motion estimation algorithm and architecture design for H.264/AVC,” in Proc IEEE Asia Pacific Conf. Circuits Syst., Dec. 2006, pp. 578–581
    [14] C. Yang, S. Goto, and T. Ikenaga, “High performance VLSI architecture of fractional motion estimation in H.264 for HDTV,”in Proc. IEEE Int. Symp. Circuits Syst.,May 2006, pp. 2605–2608
    [15] Yu-Kun Lin, Chia-Chun Lin, Tzu-Yun Kuo, and Tian-Sheuan Chang, “A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video,” IEEE trans. On Circuits and Systems vol. 55 , pp 1526-1535, Jul. 2008
    [16] T-C.Chen, S-Y. Chien, Y-W. Huang, C-H. Tsai, C-Y, Chen, T-W. Chen,and L-G.Chen, “Analysis and Architecture Design of an HDTV720p 30 Frames/s H.264/AVC Encoder”, IEEE Transactions on CSVT VOL. 16,pp. 673-687, No. 6, JUNE 2006.

    無法下載圖示 校內：2022-07-10公開
    校外：不公開
    電子論文尚未授權公開，紙本請查館藏目錄
    QR CODE