影像壓縮技術越來越重要，各種視訊壓縮標準如MPEG-2、H.264/AVC、VC-1已相繼被提出，且目前的消費性產品大多支援多格式視訊解碼。雖可針對各項標準設計相對應之電路並於設計完成後加以整合，但此法亦會導致成本過高以及使用率過低之問題。本論文設計一支援MPEG-2、H.264/AVC、VC-1多重視訊解碼應用的反轉換架構，此電路採用兩組ㄧ維反轉換運算電路來支援MPEG-2 8×8二維反離散餘弦轉換，H.264/AVC 4×4以及VC-1 8×8、8×4、4×8、4×4整數反轉換。此外更進一步採用移位器與加法器取代乘法器來降低電路面積，並以Verilog HDL實現此架構的RTL程式碼，最後採用TSMC 0.18 m製程來合成，其工作頻率可達108MHz並支援2K1080解晰度。
爲了將我們實現之IP與多重視訊解碼器進行整合並達到軟、硬體協同設計及驗證，我們使用ARM RealView Platform Baseboard作為雛型驗證平台。首先，我們針對所設計之多重標準反轉換架構設計與AMBA2.0 匯流排相容的AHB Slave介面，並爲我們的電路設計ㄧLinux 驅動程式，以實現並簡化軟硬體間的溝通介面；軟體方面，我們分別使用U-boot與Embedded Linux 作為開機管理程式與作業系統，並修改ㄧ多媒體軟體播放器(Movie Player,MPlayer)，將原始碼中之反轉換運算置換成呼叫先前已完成之反轉換電路驅動程式，此法即是將原本由軟體進行之運算改以硬體電路完成，由模擬結果可發現，整體執行時間可降低約29%，此外此軟硬體驗證平台亦可做為日後設計之多重視訊解碼矽智產整合及驗證所需。

Recently years, video compression technologies have received increasing attention. Many video compression standards such as MPEG-2, H.264/AVC and VC-1 have been proposed, therefore, many consumer digital products will support multi- standard video decoding. Alternatively we can design IPs independently for each standard and then combine them intuitively with little effort. However this may results in high hardware cost and low utilization. In this thesis we propose an architecture which supports multi-standard inverse-transformation, including MPEG-2, H.264/AVC and VC-1. In our design, we adopt two 1-D inverse-transformation (1×4) circuit to address 8×8 inverse discrete cosine transformation(IDCT) in MPEG-2, 4×4 inverse integer transformation in H.264/AVC and 8×8, 8×4, 4×8 and 4×4 inverse integer transformation in VC-1. Moreover, the multipliers are replaced with shifters and adders to further reduce hardware cost. We implement our circuit with Verilog, and then synthesize our design by using TSMC 0.18 m CMOS technology. The maximum operating frequency of our design is 108 MHz and our circuit can real-timely decode video sequence under 2K1080 resolution.
In order to integrate our design into multi-standard video decoding system, we use ARM RealView Platform Baseboard as our HW/SW co-simulation platform. First, we additionally design an AHB slave interface and Linux driver for our design. As for software we choose U-boot and embedded Linux as our boot-loader and operation system (OS) respectively. To achieve HW/SW co-simulation, we replace the source code of inverse transform in MPlayer by the Linux driver of our inverse transform circuit. It means that the operations of inverse transform are accomplished by the HW IP instead of software. From the experimental result, the decoding time can be reduced by 29% after our replacement. Moreover, the oncoming designs for multi-standard video decoding can also be integrated into this HW/SW co-simulation platform.

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