功率因數校正器用於降低輸入電流諧波失真及提高功率因數，傳統升壓型功率因數校正器於高功率應用時，其全橋整流二極體會造成較高的導通損失而降低效率，利用無橋式功率因數校正器可改善此缺點。本文主要研究無橋式圖騰柱功率因數校正器操作於連續導通模式，並應用疊接氮化鎵功率元件實現，以提高系統效率及功率密度。本文首先說明無橋式圖騰柱功率因數校正器電路之動作模式並分析其穩態特性。最後製作一實驗雛型電路以驗證理論分析，並以數位訊號處理器TMS320F28335實現平均電流法之功因校正控制，系統規格之輸入電壓90-264 Vrms，輸出電壓為400 Vdc，額定功率為1600 W。實驗結果顯示系統最高效率可達98.4 %，於額定負載時其輸入電壓為110 V與220 V之THDi分別為7.1%及9.8%，而功率因數分別可達0.997及0.998。

A power factor corrector (PFC) is used to reduce total input current harmonic distortion for high power factor. However, the full-bridge rectifier diodes of conventional boost PFCs will cause higher conduction losses and reduce efficiency in high-power applications. In this thesis, a bridgeless totem-pole PFC operated in continuous conduction mode is investigated and implemented with cascaded GaN power devices for improving system efficiency and power density. The operating principles and steady-state analyses are presented. Finally, a prototype is built to verify the theoretical analyses, and digital signal processor TMS320F28335 is used to realize the average current mode PFC control. The system specifications include an input voltage of 90-264 Vrms, output voltage of 400 Vdc, and rated power of 1600 W. Experimental results show that the maximum efficiency of the system can reach 98.4%. When the input voltages are 110 V and 220 V, the THDi and power factor are 9.8% and 0.997, and 7.1% and 0.998, respectively.

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