本論文提出一個擁有偏移背景校正的八位元每秒取樣十六億次的快閃與逐漸趨近式時間交錯型類比數位轉換器。透過混合(Hybrid)架構結合快閃類比數位轉換器(Flash ADC)以及逐漸趨近式類比數位轉換器(SAR ADC)，讓單一通道的操作速度得以大幅提升，而此兩者架構間所產生的不匹配錯誤量則採用冗餘演算法(Redundancy Algorithm)來加以克服。憑藉著高速的子通道優勢，所需要的規格只需要四個子通道即可達成，而通道間的取樣時間偏移(Timing-skew)則採用改良的取樣與保持電路(Track-and-Hold Circuit)盡可能降低；對於通道間電壓偏移不匹配(Offset Mismatch)的問題，本論文提出了「上板交換偵測」(Top-plate Swapping Detection)來協助完成校正。本設計以台積電40奈米CMOS製程實作測試晶片，其核心電路面積佔0.23mm2。當晶片操作在輸入電壓1.1伏特與取樣速度十六億次時，量測到本晶片在低輸入頻率下能夠達到45.83 dB的失真比(SNDR)，而在奈奎斯特(Nyquist-rate)輸入頻率下，可以達到40.58 dB的失真比，其換算得到的轉換效率為109.52 fJ/conversion-step。因為偏移不匹配所產生的錯誤量，在經由校正後改善了7.09 dB，其不匹配量降低至0.5個位元誤差內。

This thesis presents an 8-bit 1.6-GS/s Flash-SAR time-interleaved ADC with background offset calibration. The operation speed of a single channel can be greatly improved by adopting a hybrid architecture, which combines the flash analog-to-digital converter (ADC) and the non-binary successive-approximation register (SAR) analog-to-digital converter. The mismatch errors induced from these two ADCs are tolerated by the redundancy of the non-binary SAR ADC. Thanks to the high speed sub-channel, the specification is achieved with merely four channels. The effect of timing-skew is well mitigated with the modified Track-and-Hold Circuit, and the offset mismatch is calibrated by employing the proposed “Top-plate swapping detection” technique.
The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology, of which the core circuits cover an area of 0.23mm2. When the prototype operates at a supply voltage of 1.1-V and sampling rate of 1.6-GS/s, the measurement results show the prototype achieves 45.83 dB SNDR with low input frequency and 40.58 dB SNDR with input frequency up to Nyquist-rate, which the Figure of Merit (FoM) is 109.52 fJ/conversion-step. The error induced by offset mismatch is improved 7.09 dB after the calibration and the amount of mismatch is less than 0.5 VLSB.

[1] B. Murmann, “ADC Performance Survey 1997-2018,” [Online]. Available: http://web.stanford.edu/~murmann/adcsurvey.html.
[2] D. Kumar, “Calibration of Sampling Clock Skew in High-Speed, High-Resolution Time-Interleaved ADCs,” Massachusetts Institute of Technology, June. 2015.
[3] J. L. McCreary and P. R. Gray, "All-MOS charge redistribution analog-to-digital conversion techniques. I," in IEEE Journal of Solid-State Circuits, vol. 10, no. 6, pp. 371-379, Dec. 1975.
[4] T. Kobayashi et al., ‘‘A current-controlled latch sense amplifier and a static power-saving input buffer for low-power architecture,’’ IEEE J. Solid-State Circuits, vol. 28, no. 4, pp. 523–527, April 1993.
[5] B. Wicht et al., “Yield and speed optimization of a latch-type voltage sense amplifier,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1148−1158, Jul. 2004.
[6] P. Nuzzo et al., “Noise analysis of regenerative comparators for reconfigurable ADC architectures,” IEEE Trans. Circuits and Syst. I, vol. 55, no. 6, pp. 1441–1454, Jun. 2008.
[7] Asad Abidi et al., “Understanding the regenerative comparator circuit,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2014, pp. 1–8.
130
[8] C.-C. Liu et al., “A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure,” IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731−740, Dec. 2010.
[9] Y. Zhu et al., “A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111–1121, Jun. 2010.
[10] R. Kapusta et al., “A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2013, pp. 472–473.
[11] J.-H. Tsai et al., ‘‘A 1-V, 8b, 40MS/s, 113μW Charge-Recycling SAR ADC with a 14μW Asynchronous Controller,’’ in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, June 2011, pp. 264–265.
[12] G.-Y. Huang et al., “A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers (A-SSCC), Nov. 2013. pp. 289–292.
[13] Hung-Yen Tai et al., “A 0.85fJ/conversion-step 10b 200KS/s Subranging SAR ADC in 40nm CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2014, pp. 196-198.
[14] Y.-S. Hu et al., “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s sub-ranging SAR ADC in 40nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers (A-SSCC), 2014, pp. 81−84.
[15] Y.-Z. Lin et al., “A 9-bit 150-MS/s 1.53-mW subranged SAR ADC in 90-nm CMOS,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, Jun. 2010, pp. 243–244.
[16] S.S. Wong et al,“A 2.3mW 10-bit 170MS/s Two-Step Binary-Search Assisted TimeInterleaved SAR ADC”, in Proc. IEEE Custom Integrated Circuits Conference (CICC), Apr. 2012
131
[17] C.-C. Liu et al., “A 0.35mW 12b 100MS/s SAR-assisted digital slope ADC in 28nm CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2016, pp. 462–463.
[18] Y. J. Chen et al., “A 2.02–5.16 fJ/conversion step 10-bit hybrid coarse-fine SAR ADC with time-domain quantizer in 90 nm CMOS,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 357–364, Feb. 2016.
[19] A. Sanyal et al., “A 18.5-fJ/step VCO-based 0–1 MASH ΔΣ ADC with digital background calibration” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, June 2016.
[20] J. P. Mathew et al., “A 12-bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V supply,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, 2015, pp. C66–C67
[21] Y. Chae et al., “A 6.3 W 20 bit incremental zoom-ADC with 6 ppm INL and 1 V offset,” IEEE J. Solid-State Circuits, vol. 48, no. 12, pp. 3019–3027, Dec. 2013.
[22] B. Gnen et al., “15.7 A 1.65mW 0.16mm2 dynamic zoom-ADC with 107.5dB DR in 20kHz BW,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Jan. 2016, pp. 282–283.
[23] L. Kull et al., “A 3.1mW 8b 1.2GS/s single-channel asynchronous SAR ADC with alternate comparators for enhanced speed in 32nm digital SOI CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), 2013, pp. 468−469.
[24] G. Van der Plas et al., ‘‘A 150 MS/s 133 μW 7 bit ADC in 90 nm Digital CMOS,’’ IEEE J. Solid-State Circuits, vol. 43, no. 12, pp. 2631–2640, Dec. 2008.
[25] Tao Jiang et al., “Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR ADC in 40nm CMOS,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2010, pp. 1−4.
132
[26] T. Waho et al., “Non-binary successive approximation analog-to-digital converters: A survey,” in Proc. IEEE Int. Symp. Multiple-Valued Logic (ISMVL), 2014, pp. 73–78.
[27] W. Liu et al., “A 12b 22.5/45MS/s 3.0mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), 2010, pp. 380−381.
[28] W. Liu et al., “A 12-bit 50-MS/s 3.3 mW SARADC with background digital calibration,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), 2012, pp. 1–4.
[29] F. Kuttner et al., “A 1.2-V 10-b 20-Msample/s nonbinary successive approximation ADC in 0.13-μm CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), 2002, pp. 176−177.
[30] S.-W. M. Chen et al., “A 6-bit 600-MS/s 5.3mW asynchronous ADC in 0.13 μm CMOS,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp. 2669−2680, Dec. 2006.
[31] T. Ogawa et al., “SAR ADC algorithm with redundancy,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Nov. 2008, pp. 268–271.
[32] T. Ogawa et al., “Non-binary SAR ADC with digital error correction for low power applications,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), Dec. 2010, pp. 196−199.
[33] H.-Y. Tai et al., “A 3.2 fJ/c.-s. 0.35 V 10 b 100 kS/s SAR ADC in 90 nm CMOS,” in IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, Jun. 2012, pp. 92–93.
[34] Toru Okazaki, et al., “A Design Technique for a High-speed SAR ADC Using Non-binary Search Algorithm and Redundancy,” in Proc. IEEE Asia Pacific Microwave Conference (APMC), Dec. 2013, pp. 506−508.
[35] Hyeok-Ki Hong et al., “A 7b 1GS/s 7.2mW nonbinary 2b/cycle SAR ADC with register-to-DAC direct control,” in Proc. IEEE Custom Integrated Circuits Conf. (CICC), 2012, pp. 1−4.
133
[36] C.-C. Liu et al., “A 10b 100MS/s 1.13mW SAR ADC with binary scaled error compensation,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2010, pp. 386–387.
[37] P. Harpe et al., “A 7-to-10b 0-to-4MS/s flexible SAR ADC with 6.5-to-16fJ/conversion-step,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), 2012, pp. 472−474
[38] V. Giannini et al., “An 820 μW 9b 40 MS/s noise-tolerant dynamic-SAR ADC in 90 nm digital CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2008, pp. 238–239.
[39] M.-J. E. Lee et al., ‘‘Low-power area-efficient high-speed I/O circuit techniques,’’ IEEE J. Solid-State Circuits, vol. 35, no. 11, pp. 1591–1599, Nov. 2000.
[40] M. El-Chammas et al., “A 12-GS/s 81-mW 5-bit Time-Interleaved Flash ADC With Background Timing Skew Calibration,” IEEE J. Solid-State Circuits, vol. 46, no. 4, pp. 838-847, Mar. 2011.
[41] A. Nazemi et al., “A 10.3 GS/s 6 bit (5.1 ENOB at Nyquist) time-interleaved pipelined ADC using open-loop amplifiers and digital calibration in 90 nm CMOS,” IEEE Symp. VLSI Circuits (SOVC) Dig. Tech. Papers, 2008, pp. 18–19.
[42] C.-H. Chan et al, “A 6 b 5 GS/s 4 interleaved 3 b/cycle SAR ADC,” IEEE J. Solid-State Circuits, vol. 51, no. 2, pp. 365–377, Feb. 2016
[43] B. Sung et al., “A 6 bit 2 GS/s flash-assisted time-interleaved (FATI) SAR ADC with background offset calibration,” in Proc. IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers (A-SSCC), Nov. 2013, pp. 281–284.
[44] Stepanovic, D. and Nikolic, B.”A 2.8 GS/s 44.6 mW time-interleaved ADC achieving 50.9 dB SNDR and 3 dB effective resolution bandwidth of 1.5 GHz in 65 nm CMOS”, in IEEE J. Solid-State Circuits, vol. 48, Issue. 4, pp. 971–982, Jan. 2013.
134
[45] B. R. S. Sung et al, “A 21fJ/conv-step 9 ENOB 1.6GS/S 2× time-interleaved FATI SAR ADC with background offset and timing-skew calibration in 45nm CMOS” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2018, pp.1-3
[46] K. Poulton et al., “A 20 GS/s 8 b ADC with a 1 MB memory in 0.18 /spl mu/m CMOS,” in Proc. IEEE International Solid-State Circuits Conference Dig. Tech. Papers (ISSCC), Feb. 2003, pp. 318-496
[47] P. J. A. Harpe et al., “A 0.47-1.6mW 5-bit 0.5-1 GS/s Time-Interleaved SAR ADC for Low-Power UWB Radio,” IEEE J. Solid-State Circuits, vol. 47, no. 7, pp. 1594–1602, July. 2012.
[48] P. Harpe et al., “Calibration of Ultra Low-Power Time-Interleaved SAR ADCs,” in Proc. IEEE New Circuits and Systems Conference Dig. Tech. Papers (NEWCAS), 2012, pp. 361−364.
[49] H. Hu, Y. Cheng and S. Chang, "A 10-bit 1-GS/s 2x-Interleaved Timing-Skew Calibration Free SAR ADC," 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, 2019, pp. 1-5.
[50] M. Dessouky et al., “Input switch configuration suitable for rail-to-rail operation of switched opamp circuits,” Electron. Lett., vol. 35, pp. 8–10, Jan. 1999.
[51] G. Huang et al., “A fast bootstrapped switch for high-speed high-resolution A/D converter,” in Proc. IEEE Asia Pacific Conf. Circuits Syst. (APCCAS), 2010, pp. 382–385.
[52] Y. Zhu et al., “An 11b 900 MS/s Time-Interleaved Sub-ranging Pipelined-SAR ADC,” in Proc. IEEE Eur. Solid-State Circuits Conference Dig. Tech. Papers (ESSCIRC), Sep. 2014, pp. 211-214
135
[53] C. C. Liu et al., “A 10-bit 320-MS/s low-cost SAR ADC for IEEE 802.11ac applications in 20-nm CMOS,” IEEE Asian Solid-State Circuits Conference Dig. Tech. Papers (A-SSCC), Nov. 2014, pp. 77–80
[54] T. Constandinou, J. Georgiou, Micro-optoelectromechanical tilt sensor, Jour- nal of Sensors 2008 (2008) (Article ID 782764, 7 pages, April).
[55] C.H. Kuo et al., “A 10-bit 120-MS/s SAR ADC with Compact Architecture and Noise Suppression Technique”
[56] G.-Y. Huang et al., “A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm CMOS,” in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2013. pp. 289–292.
[57] J. A. McNeill et al., “Split ADC calibration for all-digital correction of time-interleaved ADC errors,” IEEE Trans. Circuits and Systems I: Express Briefs, vol. 56, no. 5, pp. 344–348, May 2009.
[58] T. Miki, T. Ozeki and J. Naka, "A 2GS/s 8b time-interleaved SAR ADC for millimeter-wave pulsed radar baseband SoC," 2016 IEEE Asian Solid-State Circuits Conference (A-SSCC), Toyama, 2016, pp. 5-8.
[59] N. Le Dortz et al., "A 1.62GS/s time-interleaved SAR ADC with digital background mismatch calibration achieving interleaving spurs below 70dBFS," 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), San Francisco, CA, 2014, pp. 386-388.
[60] S. Kundu et al., "A 1.2 V 2.64 GS/s 8bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN," Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, San Jose, CA, 2014, pp. 1-4.