本文提出一款應用於心音生理訊號感測晶片的雜訊整形逐次逼近型類比數位轉換器（Noise-Shaping SAR ADC）。由於心音感測器需要擷取生理訊號並將其轉換為高準確度與高解析度的數位訊號，為適用於穿戴式裝置，系統同時必須具備低功耗特性，以確保臨床診斷與健康監測的可靠性。三角積分調變類比至數位轉換器(Sigma-Delta ADC)應用於傳統心音感測器，但它會產生大量靜態功耗，架構也不利於製程演進，本文所提出的雜訊整形SAR ADC採用被動式積分器進行雜訊整形，可以達到高解析度同時維持低功耗，有效解決此問題；此外，在其雜訊轉移函數（NTF）中額外引入一個 (-0.8, 0) 的極點，以增強低頻雜訊抑制效果。本文提出一種8×被動增益的方法實現雜訊整形達成極點最佳化，該方法結合傳統的多輸入比較器 [12] 與電容堆疊技術 [2]，有效降低多輸入比較器帶來的雜訊與功耗，同時也減輕寄生電容對整體性能的影響。本設計採用台積電 180 奈米製程實現，模擬結果顯示，所提出的雜訊整形 SAR ADC 在 10 kHz 頻寬下可達到88.21 dB 的訊雜比與失真比（SNDR），其 Schreier FOM 為 167.87 dB，Walden FOM 為 256.63 fJ/conv.-step。

This paper presents a noise-shaping Successive Approximation Register (SAR) ADC as the analog front-end (AFE) for a heart sound physiological signal sensing chip. Since heart sound sensors must capture physiological signals and convert them into high-accuracy and high-resolution digital signals, these digital outputs are provided to subsequent digital signal processors and AI accelerators. The system must also operate with low power consumption to be suitable for wearable devices. Therefore, the analog-to-digital converter is designed to meet the requirements of high resolution and low power, ensuring the reliability of clinical diagnosis and health monitoring. To meet the low power and high resolution requirements of heart sound sensing, the noise-shaping SAR ADC proposed in this paper adopts a passive integrator to perform noise shaping. Additionally, a pole at (-0.8, 0) is added in the noise transfer function (NTF) to enhance low-frequency noise attenuation, thereby effectively improving the ADC resolution. To achieve pole optimization, this paper proposes an 8× passive gain method to implement noise shaping. This approach combines the traditional multi-input comparator [12] and capacitor stacking [2], effectively reducing the noise and power consumption of the multi-input comparator while mitigating the parasitic capacitance's impact on overall performance. This design is fabricated in TSMC 180 nm technology; the post-layout simulation results reveal that the proposed noise-shaping SAR ADC can achieve a signal-to-noise and distortion ratio (SNDR) of 88.21 dB in the bandwidth of 10 kHz. The Schreier figure of merit (FoM) and the Walden FoM are 167.87 dB and 256.63 fJ/conv.-step, respectively.

[1] H. Zhuang et al., "A Second-Order Noise-Shaping SAR ADC With Passive Integrator and Tri-Level Voting," in IEEE Journal of Solid-State Circuits, vol. 54, no. 6, pp. 1636-1647, June 2019.
[2] J. Liu et al., "A 90-dB-SNDR Calibration-Free Fully Passive Noise-Shaping SAR ADC With 4× Passive Gain and Second-Order DAC Mismatch Error Shaping," IEEE Journal of Solid-State Circuits, vol. 56, no. 11, pp. 3412-3423, Nov. 2021.
[3] H. Wang and G. C. Temes, "A Second-Order Passive Noise-Shaping SAR ADC With 4× Passive Gain and A Two-Input-Pair Comparator," in Proc. 2022 IEEE International Symposium on Circuits and Systems (ISCAS), Austin, TX, USA, 2022.
[4] H. Zhang et al., "A 2.5-MHz BW, 75-dB SNDR Noise-Shaping SAR ADC With a 1st-Order Hybrid EF-CIFF Structure Assisted by Unity-Gain Buffer," IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 30, no. 12, pp. 1928-1932, Dec. 2022.
[5] Y. Song, C. -H. Chan, Y. Zhu, L. Geng, S. -P. U. and R. P. Martins, "Passive Noise Shaping in SAR ADC With Improved Efficiency," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 26, no. 2, pp. 416-420, Feb. 2018, doi: 10.1109/TVLSI.2017.
[6] L. Jie et al., "An Overview of Noise-Shaping SAR ADC: From Fundamentals to the Frontier," in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 149-161, 2021.
[7] Hariprasath, V. et al. “Merged capacitor switching based SAR ADC with highest switching energy-efficiency.” Electronics Letters 46 (2010): 620-621.
[8] P. Payandehnia et al., "Fully Passive Third-Order Noise Shaping SAR ADC," Electronics Letters vol. 53 No. 8 pp. 528-530, 2017.
[9] C. -C. Liu, S. -J. Chang, G. -Y. Huang and Y. -Z. Lin, "A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure," IEEE J. Solid-State Circuits, vol. 45, no. 4, pp. 731-740, April 2010.
[10] Q. Zhang, N. Ning, J. Li, Q. Yu, K. Wu and Z. Zhang, "A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator," IEEE Trans. Very Large Scale Integration (VLSI) Syst., vol. 29, no. 1, pp. 227-231, Jan. 2021.
[11] Q. Zhang et al., "A 13-Bit ENOB Third-Order Noise-Shaping SAR ADC Employing Hybrid Error Control Structure and LMS-Based Foreground Digital Calibration," IEEE J. Solid-State Circuits, vol. 57, no. 7, pp. 2181-2195, July 2022.
[12] W. Guo and N. Sun, “A 12b-ENOB 61µW noise-shaping SAR ADC with a passive integrator,” ESSCIRC Conference 2016: 42nd European Solid-State Circuits Conference, Lausanne, Switzerland, 2016, pp. 405-408
[13] H. Zhang, N. Li, Z. Jiao, J. Zhang, X. Wang and H. Zhang, "A 1st-Order Passive Noise-Shaping SAR ADC with Improved NTF Assisted by Comparator Gain Calibration," 2021 IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, 2021, pp. 1-5
[14] Z. Chen, M. Miyahara, and A. Matsuzawa, “A 9.35-ENOB, 14.8 fJ/conv.- step fully-passive noise-shaping SAR ADC,” in Proc. IEEE Symp. VLSI Circuits (VLSI Circuits), Jun. 2015, pp. C64–C65
[15] J. Liu, D. Li, Y. Zhong, X. Tang and N. Sun, " A 250kHz-BW 93dB-SNDR 4th-Order Noise-Shaping SAR Using Capacitor Stacking and Dynamic Buffering," IEEE Int. Solid- State Circuits Conf. (ISSCC), San Francisco, CA, USA, 2021
[16] Y. -H. Hwang, Y. Song, J. -E. Park and D. -K. Jeong, "A 0.6-to-1V 10k-to-100kHz BW 11.7b-ENOB Noise-Shaping SAR ADC for IoT sensor applications in 28-nm CMOS," 2018 IEEE Asian Solid-State Circuits Conference (A-SSCC), Tainan, Taiwan, 2018, pp. 247-248
[17] J. Fredenburg and M. Flynn, "A 90MS/s 11MHz bandwidth 62dB SNDR noise-shaping SAR ADC," 2012 IEEE International Solid-State Circuits Conference, San Francisco, CA, USA, 2012, pp. 468-470
[18] X. Tang et al., "A 13.5-ENOB, 107-μW Noise-Shaping SAR ADC With PVT-Robust Closed-Loop Dynamic Amplifier," in IEEE Journal of Solid-State Circuits, vol. 55, no. 12, pp. 3248-3259, Dec. 2020
[19] J. Liu, X. Wang, Z. Gao, M. Zhan, X. Tang and N. Sun, " A 40kHz-BW 90dB-SNDR Noise-Shaping SAR with 4× Passive Gain and 2nd-Order Mismatch Error Shaping," 2020 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2020, pp. 158-160
[20] World Health Organization, "Cardiovascular diseases (CVDs)", June 11, 2021. [Online]. Available: https://www.who.int/en/news-room/fact-sheets/detail/cardiovascular-diseases-(cvds).
[21] Y. -Z. Lin, C. -Y. Lin, S. -C. Tsou, C. -H. Tsai and C. -H. Lu, "A 40MHz-BW 320MS/s Passive Noise-Shaping SAR ADC With Passive Signal-Residue Summation in 14nm FinFET," 2019 IEEE International Solid-State Circuits Conference - (ISSCC), San Francisco, CA, USA, 2019, pp. 330-332
[22] Analog Device, AD8232, Single-Lead, Heart Rate Monitor Front End.
[23] J. Xu, S. Mitra, A. Matsumoto, S. Patki, C. V. Hoof, K. A. A. Makinwa, and R.F.Yazicioglu, “A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks,” IEEE J. Solid-State Circuits, vol. 49, no. 9, pp. 2005–2016, Sep. 2014.
[24] S. Y. Lee, J. H. Hong, C. H. Hsieh, M. C. Liang, S. Y. C. Chien, K. H. Lin, "Low-power wireless ECG acquisition and classification system for body sensor networks," IEEE J. Biomed. Health Informat., vol. 19, no. 1, pp. 236-246, Jan. 2015.
[25] S. Tannirkulam Chandrasekaran, S. P. Bhanushali, S. Pietri and A. Sanyal, "OTA-Free 1–1 MASH ADC Using Fully Passive Noise-Shaping SAR & VCO ADC," in IEEE Journal of Solid-State Circuits, vol. 57, no. 4, pp. 1100-1111, April 2022