因為系統複雜度的提高，以元件為基礎的設計就期望能用來降低設計成本與時間，但是因為每個元件的介面特性不一樣，所以便需要使用介面電路來做整合。介面電路的設計是非常消耗時間而且容易產生錯誤的，因此自動化的合成與驗證在介面電路上是非常重要的。

　　在本篇論文中，我們針對組合邏輯介面，提出一個介面合成演算法，演算法的輸入是兩個元件的介面資訊，輸出是一個可以整合兩個元件的組合邏輯介面電路。我們的演算法主要分成兩個部份：在第一個部份中，我們提出一個啟發式演算法(heuristic algorithm)，此演算法可以在考慮介面電路的接線面積與動態功率損耗最小的情況下，決定元件之間接腳對接腳的連接。第二個部份，我們使用一個新穎的解碼方法去合成一個必須使用外加邏輯閘來連接的元件介面。實驗的結果顯示我們的演算法具有效率。

　　As system design becomes complex, component-based design is expected to reduce design cost and time-to-mark. However, the components may have different interface characteristics; they need to be integrated by using interface circuits. The design of interface circuitry is a timing consuming and error-prone process. Therefore, automatic synthesis and verification are very important in the interface circuit design.

　　In this thesis we propose an interface synthesis algorithm for combinational interface. The algorithm accepts the interface characteristics of two components as input and generates a combinational interface circuit such that two components can be integrated. Our algorithm consists of two phases: 1.) Phase I, a heuristic algorithm was presented to determine the direct connection such that the wiring area and dynamic power consumption can be minimized in resulting interface circuit. 2.) Phase II, we use a novel encoding method to synthesize the connection between components which require additional gates. Experiments demonstrate the efficiency of our algorithm.

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