在測試積體電路的方法裡，採用環型自我測試路徑 (circular self-test path) 的內建自我測試架構 (built-in self-test) 是一個很吸引人的技術。這種測試架構能同時進行壓縮電路輸出響應 (output response) 與產生測試向量 (test pattern)，不需要一個額外的響應分析器 (response analyzer)。另外，其它文獻也指出，可以利用電路的內部響應來產生特定測試向量。
我們在本篇論文提出一個嶄新的內建自我測試方法。其中一個特殊向量產生器可以壓縮電路的輸出響應並接著產生新的測試向量給電路。提出的方法主要包含兩個技術以提高偵測錯誤能力。第一，利用電路內部接線產生特定測試向量，不需要任何儲存裝置，第二，插入觀察點 (observation points) 來提高隨機向量的偵測錯誤能力。
由實驗結果得知，我們的方法在ISCAS及IWLS標準測試電路可以達到百分之百的錯誤覆蓋率，而且平均上，需要的電路內部接線 (含觀察點) 分別只佔所有接線的0.0837%及0.0303%，閘極面積增長分別只有2.27%和1.79%。另外，我們提出的方法也可以大幅減少分析電路的輸出響應所需要的硬體面積。

The built-in self-test (BIST) scheme which adopts circular self-test path (CSTP) is an attractive technique for testing integrated circuits. It can compact output response of the circuit under test (CUT) and generate a new pattern concurrently. As a result, it does not required an additional module for response analysis. Moreover, some papers use internal response from the CUT to generate deterministic patterns.
In this thesis, a new BIST scheme is proposed, which adopts a special test generator that can generate patterns and compact output response of the CUT. And, the proposed method utilizes very few internal nets of the CUT to generate all required data without any storage requirement. In addition, observation point insertion is employed to increase random testability of faults.
Experimental results show that the proposed approach can achieve 100% fault coverage by average 0.0837% and 0.0303% of internal nets that include inserted observation points and with average 2.27% and 1.79% gate area overhead on ISCAS and IWLS benchmark circuits, respectively. In addition, our approach can reduce the hardware about response compaction significantly.

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