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研究生: 張峻瑄
Chang, Chun-Hsuan
論文名稱: 變壓器回授低雜訊放大器與IEEE802.11ac超低相位雜訊壓控盪器之研製
Implementation of Low Noise Amplifier with Transformer Feedback and Low Phase Noise Voltage Controlled Oscillator for 802.11ac
指導教授: 張志文
Chang, Chih-Wen
王永和
Wang, Yeong-Her
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 104
中文關鍵詞: 高隔離度低雜訊放大器壓控振盪器平衡-不平衡電路
外文關鍵詞: high isolation, low noise amplifier, voltage controlled oscillator, balanced-unbalanced circuit (balun)
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  • 本論文首先使用TSMC 0.18μm CMOS製程,實現高隔離度低雜訊放大器,本次設計主要利用變壓器回授機制消除米勒電容,以提高反向隔離度與縮小整體晶片面積。經量測後變壓器回授之低雜訊放大器的增益在射頻頻率操作於23GHz為10.2 dB,反向隔離度高達50dB,雜訊指數為5.2dB,功率消耗為5.4mW,晶片面積為0.47×0.47mm2。
      第二部份延續先前提出的低雜訊放大器使用TSMC 90nm CMOS製程,實現寬頻低雜訊放大器,以寬頻負載耦合諧振腔方式改善毫米波頻段之低雜訊放大器。模擬之寬頻低雜訊放大器的增益在射頻頻率操作於54-67 GHz為16.1dB,雜訊指數為5.5dB,功率消耗為10.2mW,晶片面積為0.5×0.5mm2。
      第三部份使用TSMC 0.18μm CMOS製程,實現低功耗壓控振盪器,以閘基耦合技術,同時耦合閘極與基體,使等效轉導增大而降低相位雜訊與功率消耗,並加入差動壓控技術來改善壓控振盪器的相位雜訊特性並不額外消耗電路功率。量測之低功耗壓控振盪器在射頻頻率操作於4.91-5.45G Hz,輸出功率為0.97dBm,相位雜訊為-134.3 dBc/Hz,功率消耗為1.56 mW,優化指數(FOM)高達-196.5 dBc/Hz,晶片面積為0.6×0.6mm2。
      第四部份使用Transcom 0.25μm GaN PHEMT製程,實現具抑制二次諧波能力之微型化平衡-不平衡電路,本次設計利用兩組耦合線之耦合來達到兩輸出端的差動訊號,並於輸入端加入電感來達到抑制二次諧波優點。經量測後微小化巴倫電路在射頻頻率操作於10GHz,反射損耗為-10.3dB,插入損耗為-4.5dB,相位差為180°±2°,二次諧波抑制為-50dB,晶片面積為0.7×0.83mm2。

    A high isolation low noise amplifier (LNA) by using the transformer feedback to neutralize the Miller capacitance is implemented by a TSMC 0.18 μm CMOS process. High isolation and reduced chip size can be achieved. The measured results show that the gain is 10 dB, isolation is higher than 50 dB, noise figure is 5.2 dB, and the power consumption is 5.4 mW at 23 GHz. The chip size is 0.47×0.47 mm2.
    A millimeterwave LNA using the LC tank to enhance the broadband operation implemented by a TSMC CMOS 90 nm process is proposed. The simulated results show that the gain is 16.1 dB, noise figure is 5.5 dB, and the power consumption is 10.2 mW from the RF bandwidth 54 to 67 GHz. The chip size is 0.5×0.5mm2.
    To enhance the performance of phase noise and power consumption, the voltage controlled oscillator employing the body bias technology to couple the gate and body implemented by a TSMC 0.18 μm CMOS process is presented. Differential technology is also employed to improve the phase noise. The measured results show that the output power is 0.97 dBm, phase noise is -134.3 dBc/Hz, power consumption is 1.56 mW, and the figure of merit is -196.5 dBc/Hz from the RF bandwidth 4.91to 5.45GHz. The chip size is 0.6×0.6 mm2.
    A miniaturized balanced-unbalanced circuit (balun) with second harmonic suppression is achieved by two coupled line and inductor implemented by a Transcom 0.25μm GaN HEMT process. The measured results show that the return loss is 10.3 dB, insertion loss is 4.5 dB, phase difference between two ports is 180°±2°, and the second harmonic suppression is as high as 50dB at 10 GHz. The chip size is 0.7×0.83 mm2.

    中文摘要 I Abstract III 致謝 V 目錄 VII 圖目錄 IX 表目錄 XII 第一章 緒論 1 1.1 研究背景 1 1.2 射頻前段接收機 4 1.3 論文架構 5 第二章 低雜訊放大器 6 2.1 低雜訊放大器簡介 6 2.1.1 雜訊指數 7 2.2 應用於K-band之雙回授式低雜訊放大器 9 2.2.1 研究動機 9 2.2.2 電路架構設計 14 2.2.3 模擬與量測結果 17 2.2.4 結論 26 2.3 應用於V-band之低功耗、高增益低雜訊放大器 27 2.3.1 研究動機 27 2.3.2 電路架構設計 28 2.3.3 模擬結果 32 2.3.4 結論 39 第三章 壓控振盪器 42 3.1 壓控振盪器簡介 42 3.1.1 相位雜訊來源 46 3.1.2 相位雜訊模型 48 3.2應用於802.11ac之低功耗壓控振盪器 58 3.2.1 研究動機 58 3.2.2 電路架構設計 58 3.2.3 模擬與量測結果 65 3.2.4 結論 73 第四章 微型化平衡-不平衡轉換器 74 4.1 平衡-不平衡轉換器簡介 74 4.2 基本微帶線原理 75 4.3 基本平行耦合線原理 76 4.4 具抑制二次諧波之微型化平衡-不平衡轉換器 79 4.4.1 電路架構設計 79 4.4.2 模擬與量測結果 90 4.4.3 結論 96 第五章 結論與未來研究 97 5.1結論 97 5.2未來研究 98 文獻參考 100

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