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研究生： 余承燁
Yu, Cheng-Yeh
論文名稱： 網路卸載引擎的設計與實作
Design and Implementation of a Network Offload Engine
指導教授： 陳中和
Chen, Chung-Ho
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電腦與通信工程研究所
Institute of Computer & Communication Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 145
中文關鍵詞： 網路協定 、ICMP 、ARP 、IP 、網路卸載引擎 、TCP/IP 協定 、TCP 、使用者資料包協定 、傳輸控制協定 、網際網路控制訊息協定 、位址解析協定 、UDP
外文關鍵詞： Nios, ARP, SOPC builder, TCP, TCP/IP Offload Engine, SoC, TOE, TCP/IP, ICMP, IP, UDP
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    • 　　在這篇論文裡，我們提出了一個在高速網路以及有限硬體資源下的嵌入式系統會遇到的效能問題，並設計了一個TCP/IP處理模組，TCP/IP卸載引擎(TCP/IP Offload Engine, TOE)。此模組可以應用在SoC系統或是強化的網路卡中，並取代以CPU執行程式來處理網路封包的方案，使用特定功能積體電路來做封包標頭的處理。目前的設計以實現簡單標頭處理的硬體為主，需要輔以適當韌體及DMA做資料的搬移與緩衝區管理。此處理模組的特色有

    1.擁有三大功能：ping request/ reply、UDP connection 和TCP connection。
    2.實現ARP、IP、ICMP、UDP、以及TCP的標頭處理模組。
    3.硬體TCP/UDP連線管理機制(8 concurrent connections)。
    4.利用額外的硬體在搬移資料時計算IP 標頭檢查和第四層的檢查和。

    　　由於TCP/IP模組的複雜以及龐大，在撰寫此篇論文時，此設計的實作並沒有完全。但TOE模組的架構以及資料管理的機制已實作完畢，只缺少第四層處理模組的實作。本論文也利用Altera PCI Development Kit的發展環境建構了一個應用此TOE模組的SoC系統，並評估系統實現後預期的效能以及可以改進的空間。效能評估的計算顯示，只要系統運作在高於14.7MHz的時脈下，便可以達到100Mbps wire-speed的網路速度；而Altera Quartus II的時序分析(timing analysis)顯示此TOE模組可以達到的最高時脈是49MHz。

    　This thesis addresses the design of a TCP/IP hardware module which can be used in an SoC system or an enhanced Network Interface Controller (NIC). The present implementation uses a state machine-based design which performs limited TCP/IP functions along with the required firmware for data movement and buffer management. There are several features of this design.

    1.Three main functions：Ping request/ reply, UDP connection, and TCP connection management.
    2.Header processing modules for ARP, IP, ICMP, UDP, and TCP protocols are implemented in hardware.
    3.The design is capable for 8 concurrent UDP/ TCP connection management.
    4.A bypass circuit is used to handle the IP header checksum and layer 4 checksum, including verification for receiving
    datagrams and checksum calculation for transmitted datagram.

    　However, at the time of writing this thesis, the implementation is not fully accomplished. The design of the whole Offload Engine is implemented except for the layer 4 processing modules. An SoC system is made by the Altera PCI Development Kit to test the Offload Engine. The performance estimation shows that the system can process 100Mps network packets in wire-speed if the clock rate is greater than 14.7 MHz. The timing analysis shows that the clock rate of the implementation can be set to 49MHz.

    TABLE OF CONTENTS V LIST OF FIGURES VIII LIST OF TABLES XI CHAPTER 1 INTRODUCTION 1 1.1 MOTIVATION 1 1.2 GOALS OF THE OFFLOAD ENGINE 3 1.3 CONTRIBUTION OF THIS THESIS 4 CHAPTER 2 RELATED WORK 6 2.1 ASIC WITH TCP/IP FUNCTIONS 6 2.1.1 An Open TCP/IP Core for Reconfigurable Logic [6] 6 2.1.2 WIZnet Inc. – i2Chip W3100A [7] 9 2.1.3 ConnectOne Co. – iChip Internet Controller [8] 10 2.2 NETWORK INTERFACE CONTROLLER WITH EMBEDDED SOFTWARE 11 2.2.1 eDevice Inc. 11 2.2.2 Alacritech Inc. –TOE Network Interface Controller [2] [10] 12 2.2.3 Xilinx Gigabit System Reference Design [11] 13 CHAPTER 3 ARCHITECTURE 15 3.1 DESIGN SPECIFICATION 15 3.1.1 From normal TCP/IP stack to system with off load engine 15 3.1.2 Address Resolution Protocol (ARP) 18 3.1.3 Internet Protocol 20 3.1.4 Internet Control Message Protocol 24 3.1.5 User Datagram Protocol 25 3.1.6 Transmission Control Protocol 27 3.1.7 System Overview 31 3.1.8 Logical View of the Design 34 3.1.9 Physical Block Diagram 37 3.2 THE DESIGN OF SUB-MODULES 39 3.2.1 Connection Control Information (CCI) 39 3.2.2 Data Buffer Management 42 3.2.3 Structure of Buffer tables 45 3.2.4 Inner Buses 48 3.2.5 The Arbiter 52 3.2.6 16-bit checksum module 54 3.2.7 ARP table and layer 4 connection control tables 57 3.3 PROTOCOL MODULES 58 3.3.1 CPU CCI-access modules 58 3.3.2 ARP modules 60 3.3.3 IP modules 61 3.3.4 ICMP modules 64 3.3.5 UDP modules 65 3.3.6 TCP modules 67 3.4 DATAFLOW 71 3.4.1 Receiving flow 72 3.4.2 Transmitting flow 74 3.5 SOFTWARE FOR THIS OFFLOAD ENGINE 76 3.5.1 MAC-receiving-a-frame interrupt service routine 76 3.5.2 RX-DMA-request (Offload Engine Rx done) ISR 79 3.5.3 Host-needs-transmit interrupt service routine 80 3.5.4 MAC TX (Offload Engine Tx done) interrupt service routine 82 CHAPTER 4 IMPLEMENTATION 83 4.1 SYSTEM OVERVIEW 83 4.2 WHAT ARE EXACTLY IMPLEMENTED 86 4.3 FPGA DEVELOPMENT ENVIRONMENT 88 4.3.1 Introduction to the Stratix PCI Development Kit 88 4.3.2 Nios Embedded Processor Design Tools 89 4.3.3 SOPC Builder 90 4.3.4 Software developing tools 93 4.4 SYNTHESIS RESULT 93 4.5 PERFORMANCE ESTIMATION 95 4.5.1 Receiving a bit stream of single TCP connection 96 4.5.2 Receiving frames with empty payloads 98 4.5.3 Receiving bit streams of multiple TCP connections 99 4.5.4 Transmitting a TCP bit stream of single TCP connection 99 4.5.5 Transmitting frames with empty payloads 101 4.5.6 Conclusion of the performance estimation 102 CHAPTER 5 TEST AND VERIFICATION 105 5.1 THE VERIFICATION PLAN 105 5.2 THE NETWORK ANALYZER 109 5.3 NETWORK PROGRAMS 111 5.3.1 Ping 111 5.3.2 Custom Programs 112 5.4 SIMULATION RESULT 114 CHAPTER 6 CONCLUSIONS AND FUTURE WORK 115 6.1 CONCLUSIONS 115 6.2 FUTURE WORK 115 REFERENCE 117 APPENDIX A: SELF-INTRODUCTION 119 APPENDIX B: A FRAMEWORK DESIGN OF A NETWORK OFFLOAD ENGINE USING QUEUE-BASED COMMUNICATION 120

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    Computing,” IEEE Conference on Local Computer Networks 2002.
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    Alachritech, Inc. “TCP/IP Offload Network Interface Device,” United States Patent US 00434620B1,
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    TCP/IP core for reconfigurable logic,” Thesis of Electronics and Computer Engineering Department, Technical University of

    Crete, July 2001.
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    http://rfc.net/rfc791.html, September 1981.
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    Workloads” In Proc. Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads, February 2004.

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