這篇論文實現了一個每秒三十二億位元低功耗半速率時脈資料回復電路。此架構在頻率預先設定模式和資料回復模式共用兩組閘控制壓控震盪器，使串接時脈資料回復電路中之LC-tank壓控震盪器得以移除。除此之外，本論文還提出了一種主動型電感架構取代原本在晶片中需要大面積的被動電感，其在高速操作下能夠降低功率消耗和縮小晶片面積。此時脈資料回復電路使用TSMC 1P6M 0.18μm CMOS 製程做設計，核心電路面積為0.28 mm2。透過佈局後模擬的驗證，此電路在使用每秒三十二億位元 27-1的偽隨機二進制序列做測試時，總消耗功率為16.48 mW，抖動的峰對峰值與方均根值分別為15.93 ps和2.64 ps。

This thesis presents a 3.2-Gb/s low-power clock and data recovery (CDR) circuit. This proposed CDR circuit utilizes two half-rate gated voltage-controlled oscillators shared between frequency presetting and data recovery modes to remove the LC-tank voltage-controlled oscillator in a cascaded CDR. Moreover, an active inductive loading technique instead of large-area on-chip passive inductors is proposed to reduce the power consumption and silicon area in high-speed operation. This CDR circuit is designed in TSMC 1P6M 0.18-μm CMOS technology with an active area of 0.28 mm2. Post-layout simulations show that this circuit consumes 16.48 mW. Besides, the peak-to-peak jitter and rms jitter of the recovered clock are 15.93 ps and 2.64 ps for a 3.2-Gb/s 27-1 PRBS, respectively.

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