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研究生： 呂柏辰
Lu, Po-Chen
論文名稱： 基於創新的部分佔用邊角縫織之三維模塊擺置設計流程
A 3D Macro Placement Design Flow based on A Novel Partially Occupied Corner Stitching
指導教授： 林家民
Lin, Jai-Ming
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 27
中文關鍵詞： 模塊擺置 、實體設計 、三維晶片
外文關鍵詞： macro placement, physical design, 3D IC, 3-D IC
相關次數： 點閱：91  下載：10 
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    • 雖然三維晶片擺置問題已經被研究了很多年，但針對模塊合法化的研究卻很有限。由於模塊的尺寸很大，模塊擺置問題比標準邏輯閘擺置更為難，特別是在多層結構中存在預先擺置模塊時。為了在擺置時具有全域觀點，本文提出了分區最後模塊優先流程來處理適用於混合尺寸設計的三維擺置，該流程在原型擺置後進行分層，然後在標準邏輯閘擺置之前對模塊進行合法化。我們提出了一種處理三維模塊擺置的新方法，此方法由兩個步驟組成。首先根據新的 K層部分佔用邊角逢織表示法確定模塊在壓縮平面中的位置，這不僅可以保留原型擺置結果，還可以確保模塊在分層後得到合法擺置。接下來，透過 ILP 數學解法將模塊分配到各個層。實驗結果表明，我們的設計流程可以比其他流程獲得更好的結果，尤其是在具有較多預先擺置模塊的情況下。

    Although the 3D IC placement problem has been studied for many years, there exist limited researches which dedicate on the macro legalization. Due to large sizes of macros, the problem is hard than cell placement especially when preplaced macros exist in a multi-tier structure. In order to have a global view, this paper proposes the partitioning-last macro-first flow to handle 3D placement for mixed-size designs, which performs tier partitioning after placement prototyping and then legalizes macros before cell placement. We propose a novel approach to handle 3D macro placement which is composed of two steps. The first step determines locations of macros in a compressed plane based on a new representation, named K-tier Partially Occupied Corner Stitching. It not only can keep the prototyping result but also guarantees a legal placement after tier assignment of macros. Next, macros are assigned to respective tiers by ILP algorithm. Experimental results show that our design flow can obtain better solutions than other flows especially in the cases with more preplaced macros.

    摘要 II Abstract III 誌謝 IV Table of Contents V List of Tables VII List of Figures VIII Chapter 1 Introduction 1 1.1 Our Contributions 3 Chapter 2 Problem Formulation and Preliminary 5 2.1 Problem Formulation 5 2.2 Review of Congestion Map 5 Chapter 3 Our Methodology 6 3.1 Placement Prototyping in a Projection Plane 7 3.2 Tier Assignment of Standard Cells 7 3.3 TSV Placement 8 Chapter 4 K-tier Partially Occupied Corner Stitching 9 4.1 K-tier Partially Occupied Corner Stitching 9 4.2 Feasibility Conditions of K-POCS 10 4.3 Multi-partite Graph Checking 13 4.3.1 ILP-based Approach 13 4.3.2 Greedy Algorithm 14 Chapter 5 3D Macro Placement 16 5.1 Expansion of Macros 16 5.2 Macro Placement Algorithm based on K-POCS 16 5.3 Tier Assignment of Macros 17 Chapter 6 Experimental Results 19 Chapter 7 Conclusion 25 Bibliography 26

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