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研究生： 李佳欣
Lee, Chia-Hsin
論文名稱： 一個使用數位碼錯誤校正之2.5-bit/cycle十位元每秒取樣一億六千萬次的逐漸趨近式類比數位轉換器
A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC with Digital Code Error Correction
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2016
畢業學年度： 104
語文別： 英文
論文頁數： 110
中文關鍵詞： 2.5-bit/cycle 、輸入位準平移 、逐漸趨近式 、類比數位轉換器
外文關鍵詞： 2.5-bit/cycle, input level shifting, successive approximation, SAR, analog-to-digital converter, ADC
相關次數： 點閱：88  下載：6 
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    • 本論文提出一個單通道2.5-bit/cycle十位元每秒取樣一億六千萬次的逐漸趨近式類比數位轉換器。與過去的2.5-bit/cycle逐漸趨近式類比數位轉換器相比，本研究提出的輸入位準平移技巧可減少一組副數位類比轉換器的使用，並降低另外兩組副數位類比轉換器對解析度的要求；此外，數位碼錯誤校正透過簡潔的數位電路方式，實現了更大的錯誤量容忍範圍。
    本設計以台積電90奈米CMOS標準1P9M製程實作晶片，核心電路面積佔262.8μm × 420 μm。量測結果顯示，在1伏特電源供電及每秒取樣一億六千萬次的操作速度下，訊號雜訊比之最大值為53.23分貝，換算之有效位元數為8.55位元，消耗功率為1.97 mW，每次資料所消耗的能量為32.9 fJ。

    This thesis presents a single-channel 2.5-bit/cycle 10-bit 160-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC). In comparison with the conventional 2.5-bit/cycle SAR ADC, the proposed input level shifting technique saves one sub-digital-to-analog converter (sub-DAC) and relaxes the requirement on resolution for the other sub-DACs. In addition, the proposed digital code error correction provides a wider error tolerance range by a compact digital design. The proposed ADC was fabricated in TSMC 90-nm CMOS standard 1P9M process, and occupies 262.8 μm × 420 μm active area. At 1-V supply and 160-MS/s sampling rate, the measured peak signal-to-noise and distortion ratio (SNDR) is 53.23 dB. The resultant effective number of bits is 8.55 bits with power consumption of 1.97 mW. The figure-of-merit (FoM) is 32.9 fJ/conversion-step.

    Abstract II List of Figures VIII List of Tables XII Chapter 1 Introduction 1 1.1 BACKGROUND AND MOTIVATION 1 1.2 ORGANIZATION 4 Chapter 2 Fundamentals of Analog-to-Digital Converters 5 2.1 THE BASICS OF ADCS 5 2.1.1 Quantization Error 6 2.1.2 Resolution 9 2.1.3 Accuracy 9 2.2 STATIC SPECIFICATIONS 10 2.2.1 Offset Error 10 2.2.2 Gain Error 10 2.2.3 Nonlinearity 12 2.3 DYNAMIC SPECIFICATIONS 15 2.3.1 Signal-to-Noise Ratio 15 2.3.2 Signal-to-Noise and Distortion Ratio 16 2.3.3 Effective Number of Bits 16 2.3.4 Spurious Free Dynamic Range 16 2.3.5 Total Harmonic Distortion 17 2.4 TYPES OF NYQUIST RATE ADCS 18 2.4.1 Flash ADC 18 2.4.2 Pipelined ADC 20 2.4.3 Successive-Approximation Register ADC 22 Chapter 3 Introduction of SAR ADCs 23 3.1 BASICS OF SAR ADCS 23 3.1.1 The Concepts of SAR Scheme 24 3.1.2 Circuit Operation of the SAR Architecture 26 3.2 DESIGN TECHNIQUES OF SAR ADCS 29 3.2.1 Capacitor Switching Methods 29 3.2.2 Multi-bit Design techniques 37 3.3 REDUNDANCY AND ERROR TOLERANCE 43 3.3.1 Binary-Scaled Error Compensation 43 3.3.2 Half-bit Redundancy in Multi-bit Structure 46 Chapter 4 A 10-bit 160-MS/s SAR ADC 52 4.1 INTRODUCTION 52 4.2 ARCHITECTURE CONSIDERATION 54 4.2.1 The 2.5-bit/cycle Structure 55 4.2.2 Circuit Operation Procedure 58 4.3 PROPOSED TECHNIQUES 59 4.3.1 Input Level Shifting Technique 59 4.3.2 Digital Code Error Correction 64 4.4 ARCHITECTURE OF PROPOSED SAR ADC 75 4.5 CIRCUIT IMPLEMENTATION 77 4.5.1 Bootstrapped Switch 77 4.5.2 Dynamic Comparator 79 4.5.3 Digital Control Logic Circuits 81 4.5.4 Capacitor DAC Array 86   Chapter 5 Simulation and Measurement Results 88 5.1 LAYOUT AND CHIP FLOOR PLAN 88 5.2 SIMULATION RESULTS 91 5.3 DIE MICROGRAPH AND MEASUREMENT SETUP 96 5.4 MEASUREMENT RESULTS 98 Chapter 6 Conclusions and Future Works 103 Bibliography 105

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