本論文之主要目的在於探討氮化鎵化合物元件成長於矽(111)基板及圖形化基板時的影響因素，並且運用了許多方法去更一步的提升氮化鎵的磊晶品質以及元件特性。我們運用熱退火循環的技術以及插入低溫氮化鋁，成功的磊晶成長高品質氮化鎵材料於矽基板上，並且將三甲基鎵沉積於高速電子遷移率場效電晶體元件表面，藉由通入氧氣氧化形成氧化鎵介電層來改善元件特性，以及探討常關型元件的機制。最後使用條紋式圖形矽基板來磊晶製造分段式閘極高速電子遷移率場效電晶體以及奈米凹狀圖案藍寶石基板來磊晶製造發光二極體。
首先探討熱退火循環以及插入低溫氮化鋁對於磊晶品質的影響，藉由高解析X光射線繞射儀、光致發光量測系統、拉曼光譜儀及原子力顯微鏡等量測設備分析磊晶材料的品質，透過實驗進行品質改善，使用這些方法可以有效的讓磊晶層所受的應力從0.98降至0.36 GPa，且插入低溫氮化鋁層可以讓薄膜沒有裂痕的問題。最後製作出高速電子遷移率場效電晶體也顯示出高電流密度(328 mA/mm)以及低源極漏電流(3.2×10−3 mA/mm)的特性，然而其閘極漏電流仍略高(3.8×10−4 mA/mm)。
接下來使用氧氣氧化元件表面形成氧化介電層來改善元件特性，結果顯示使用此簡單的方式可以有效的讓閘極漏電流下降至1.4×10-6　mA/mm，此外，此介電層亦有鈍化層的特性，因此可以進一步提升元件電流密度。並且研製常關型元件，探討運用凹槽式閘極的缺陷以及使用氟電漿來做改良。臨界電壓可以有效地從-3.8位移至+1.1伏特, 且在閘極電壓比臨界電壓高出2伏特時電流密度為218 mA/mm。
　　最後，使用圖形化基板來改善元件特性，藉由改變成長五三比以及壓力於條紋式圖形化矽基板，可以製作出低缺陷的磊晶層，並且可以利用此條紋製作分段式閘極高速電子遷移率場效電晶體，結果顯示此結構元件的飽和電流不會因電壓升高而下降，且電流密度與使用平面式基板相比亦從297 mA/mm提升至 331 mA/mm；此外，我們也使用奈米凹狀圖案藍寶石基板來磊晶成長發光二極體元件，藉由改變凹狀圖案的蝕刻深度，可以有效的提升整體發光二極體的發光效率，隨著蝕刻深度的提升，效率可以從5.29 %提升至6.28 %，並且使用二氧化矽側壁保護層來進一步改進磊晶品質，結果顯示此方法可以有效的提升內部量子效率，因此大幅提升發光效率至11.4 %。

The main purpose of this study is to investigate the factors that interfere with the quality of GaN grown on Si (111) substrate and patterned substrate. Numerous methods were used to improve the quality of the epitaxial layer and the device characteristics. High-quality GaN was successfully grown on Si substrate by thermal cycle annealing and by inserting low-temperature AlN technique. The HEMT device characteristic was improved by using Ga2O3 as a dielectric, which was formed by trimethylgallium deposited on the surface followed by the O2 annealing process. The normally off device was also fabricated, and its mechanism was investigated. Finally, the distributed gate HEMT was fabricated on a stripe-patterned Si substrate, and LED was fabricated on concave nano-patterned sapphire substrate.
The effects of thermal cycle annealing and inserting low-temperature AlN on the epitaxial layer were investigated. The film quality was analyzed by XRD, PL, Raman, and AFM measurements. The strain was successfully decreased from 0.98 to GPa 0.36 GPa through experiments, and a crack-free surface was achieved by inserting a low-temperature AlN. The fabricated HEMT showed the characteristics of the high-drain current density (328 mA/mm) and low-drain leakage (3.2×10−3 mA/mm). However, the gate leakage showed a worse property (3.8×10−4 mA/mm).
The HEMT device characteristic was improved by using Ga2O3 as a dielectric. Ga2O3 was formed upon the deposition of trimethylgallium on the surface followed by the O2 annealing process. The simple method can effectively reduce the gate leakage current to 1.4 × 10-6　mA/mm. The dielectric layer was considered as a thin passivation to improve the drain current density. The normally off device was also fabricated to investigate the recess gate mechanism, and the device improved by fluorine plasma treatment. The threshold voltage can shift from −3.8 to +1.1 V, and the drain current density was 218 mA/mm at VGS-Vth was 2 voltage.
Finally, patterned substrate was used in this study to enhance the device characteristics. By varying the growth conditions (i.e., V/III ratio and pressure on patterned Si substrate), the low defect density epitaxial layer can be achieve and used to fabricate distributed gate HEMT. The drain current did not decrease with saturation. The drain current was improved from 297 mA/mm to 331 mA/mm compared with that grown on the planar substrate. Meanwhile, the concave nano-patterned sapphire substrate was used to develop a LED structure. By increasing the pattern etching depth, the external quantum efficiency was enhanced from 5.29% to 6.28%. Further improvement may be obtained by using SiO2 sidewall blocking layer. The results indicated that the internal quantum efficiency improved, and thus, the external quantum efficiency also improved to 11.4%.

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Bibliography-Chapter 6
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