本論文實現一個十四位元每秒二百五十億次取樣之電流源式數位類比轉換器。針對非理想來源，包含電流源電晶體不匹配、有限輸出阻抗、切換突波效應與輸入數位訊號不完整，此數位類比轉換器使用相對應的技術減輕其造成的影響，並達到高速高解析的特性。首先，對於電流源電晶體不匹配，本論文採用動態元件匹配方法以降低電流源電晶體產生之電流不匹配誤差造成的失真。其次，使用輸出阻抗補償技術以補救電流單元輸出阻抗不足造成的失真。再者，對於高速運作下產生的輸出轉換非線性，採用切換突波補償技術來得到改善。最後，由於用以驅動大量電流單元並傳輸數位訊號的前驅動器頻寬不足，將造成輸入於電流單元的數位訊號不完整而產生雜訊與失真，對此，本論文使用主動式峰化的方法來擴大前驅動器頻寬並改善數位訊號品質。
此數位類比轉換器實現於TSMC 40 nm 1P9M互補式金氧半導體製程，主動電路面積占0.4平方毫米。後模擬結果顯示，在每秒二百五十億次取樣頻率下，此數位類比轉換器從低頻至一百一十億赫茲的無雜散動態範圍可達到 > 50 dBc。

The thesis realizes a 14-bit 25-GS/s current-steering digital-to-analog converter (DAC). With the corresponding techniques, the DAC can mitigate the effect of non-ideality sources which are current-source transistor mismatch, finite output impedance, switching glitch and pre-driver bandwidth extension, achieving high-speed high-resolution characteristic. Firstly, for current source mismatch, this work utilizes dynamic element matching (DEM) to reduce the distortion caused by current mismatch error. Secondly, an output-impedance compensation (OIC) technique is adopted to remedy the distortion caused by insufficient output impedance of current cell. Additionally, regarding the output transition nonlinearity, a switching-glitch compensation (SGC) technique is used to improve the performance. Lastly, due to insufficient bandwidth of pre-driver used for driving the large number of current cells, the input digital signal of current cell will be incomplete, resulting in distortion and noise. This work adopts active peaking to extend the bandwidth of pre-driver.
The DAC is fabricated in TSMC 40-nm 1P9M CMOS process with active area 0.4 mm2. The post-simulation results show that the DAC can achieve > 50 dBc from dc to 11 GHz.

[1] “IEEE Standard Letter Designations for Radar-Frequency Bands - Redline,” in IEEE Std 521-2019 (Revision of IEEE Std 521-2002) - Redline, vol., no., pp.1-22, 14 Feb. 2020.
[2] P. Eloranta, P. Seppinen, S. Kallioinen, T. Saarela, and A. Parssinen, “A multimode transmitter in 0.13 μm CMOS using direct-digital RF modulator,” IEEE J. Solid-State Circuits, vol. 42, no. 12, pp. 2774–2784, Dec. 2007.
[3] S.-Y-S Chen, N.-S Kim, and J. Rabaey., “A 10b 600MS/s Multi-mode CMOS DAC for Multiple Nyquist Zone Operation” in IEEE Symp. VLSI Circuits Dig. Tech. Papers, Jun. 2011, pp. 1–2.
[4] C. Erdmann et al., "16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving −70.8dBc ACPR in a 20MHz channel at 5.2GHz," 2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, pp. 280-281.
[5] P. Caragiulo, O. E. Mattia, A. Arbabian and B. Murmann, "A Compact 14 GS/s 8-Bit Switched-Capacitor DAC in 16 nm FinFET CMOS," 2020 IEEE Symposium on VLSI Circuits, 2020, pp. 1-2.
[6] P. Caragiulo, O. E. Mattia, A. Arbabian and B. Murmann, "A 2x Time-Interleaved 28-GS/s 8-Bit 0.03-mm2 Switched-Capacitor DAC in 16-nm FinFET CMOS," in IEEE Journal of Solid-State Circuits, vol. 56, no. 8, pp. 2335-2346, Aug. 2021.
[7] H. M. Nguyen, J. S. Walling, A. Zhu and R. B. Staszewski, "A mm-Wave Switched-Capacitor RFDAC," in IEEE Journal of Solid-State Circuits, vol. 57, no. 4, pp. 1224-1238, April 2022.
[8] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, "Matching properties of MOS transistors," in IEEE Journal of Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.
[9] G. A. M. Van Der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert and G. G. E. Gielen, "A 14-bit intrinsic accuracy Q/sup 2/ random walk CMOS DAC," in IEEE Journal of Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.
[10] D. -H. Lee, Y. -H. Lin and T. -H. Kuo, "Nyquist-Rate Current-Steering Digital-to-Analog Converters with Random Multiple Data-Weighted Averaging Technique and QN Rotated Walk Switching Scheme," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 53, no. 11, pp. 1264-1268, Nov. 2006.
[11] H. -Y. Huang and T. -H. Kuo, "A 0.07-mm2 162-mW DAC Achieving >65 dBc SFDR and < −70 dBc IM3 at 10 GS/s With Output Impedance Compensation and Concentric Parallelogram Routing," in IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2478-2488, Sept. 2020.
[12] W. -H. Tseng, C. -W. Fan and J. -T. Wu, "A 12-Bit 1.25-GS/s DAC in 90 nm CMOS with >70 dB SFDR up to 500 MHz," in IEEE Journal of Solid-State Circuits, vol. 46, no. 12, pp. 2845-2856, Dec. 2011.
[13] K. L. Chan, J. Zhu and I. Galton, "Dynamic Element Matching to Prevent Nonlinear Distortion from Pulse-Shape Mismatches in High-Resolution DACs," in IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2067-2078, Sept. 2008.
[14] Wei-Te Lin, and Tai-Haur Kuo, “A Compact Dynamic-Performance-Improved Current-Steering DAC With Random Rotation-Based Binary-Weighted Selection,” IEEE J. Solid-State Circuits, vol. 47, no. 2, pp. 444-453, Feb. 2012.
[15] W. -T. Lin, H. -Y. Huang and T. -H. Kuo, "A 12-bit 40 nm DAC Achieving SFDR > 70 dB at 1.6 GS/s and IMD < –61dB at 2.8 GS/s With DEMDRZ Technique," in IEEE Journal of Solid-State Circuits, vol. 49, no. 3, pp. 708-717, March 2014.
[16] C.-H. Lin et al., “A 12 bit 2.9 GS/s DAC with IM3 <−60 dBc beyond 1 GHz in 65 nm CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp. 3285–3293, Dec. 2009.
[17] C. Lin et al., "A 16b 6GS/S Nyquist DAC with IMD <-90dBc up to 1.9GHz in 16nm CMOS," 2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, pp. 360-362.
[18] D. -H. Lee, T. -H. Kuo and K. -L. Wen, "Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 56, no. 2, pp. 137-141, Feb. 2009.
[19] H. -Y. Huang, X. -Y. Chen and T. -H. Kuo, "A 10-GS/s NRZ/Mixing DAC With Switching-Glitch Compensation Achieving SFDR >64/50 dBc Over the First/Second Nyquist Zone," in IEEE Journal of Solid-State Circuits, vol. 56, no. 10, pp. 3145-3156, Oct. 2021.
[20] D. Yamazaki, T. Yamamoto, M. Horinakal, H. Nomura, K. Hashimoto and H. Onodera, "A 25GHz clock buffer and a 50Gb/s 2:1 selector in 90nm CMOS," 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, pp. 240-525.
[21] K. Zheng, Y. Frans, K. Chang and B. Murmann, “A 56 Gb/s 6 mW 300 um2 inverter-based CTLE for short-reach PAM2 applications in 16 nm CMOS,” 2018 IEEE Custom Integrated Circuits Conference (CICC), 2018, pp. 1-4.
[22] S. S. Mohan, M. D. M. Hershenson, S. P. Boyd and T. H. Lee, "Bandwidth extension in CMOS with optimized on-chip inductors," in IEEE Journal of Solid-State Circuits, vol. 35, no. 3, pp. 346-355, March 2000.
[23] D. Gruber et al., "10.6 A 12b 16GS/s RF-Sampling Capacitive DAC for Multi-Band Soft-Radio Base-Station Applications with On-Chip Transmission-Line Matching Network in 16nm FinFET," 2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, pp. 174-176.
[24] S. Su and M. S. Chen, "A 16-bit 12-GS/s Single-/Dual-Rate DAC With a Successive Bandpass Delta-Sigma Modulator Achieving <−67-dBc IM3 Within DC to 6-GHz Tunable Passbands," in IEEE Journal of Solid-State Circuits, vol. 53, no. 12, pp. 3517-3527, Dec. 2018.
[25] J. Kim et al., “A 224-Gb/s DAC-Based PAM-4 Quarter-Rate Transmitter With 8-Tap FFE in 10-nm FinFET,” in IEEE Journal of Solid-State Circuits, vol. 57, no. 1, Jan. 2022.