隨著電路複雜性和測試資料量的增加，EDT測試壓縮技術已在工業中得到廣泛採用，以降低測試成本。這種可測試設計(DFT)方法的挑戰之一是確定一組最佳參數，例如掃描鏈的數量、掃描通道數量與功率預算…等，使其能夠在滿足各種其他約束的同時達到最高的測試覆蓋率與最小的測試資料量。為了快速實現最佳壓縮配置，在這篇論文中，我們使用TensorFlow作為深度學習的框架，以評估在給定的電路參數集下採用EDT時電路的測試覆蓋率和測試資料量。根據估計的資料，還可以預測最佳的測試架構。與當前使用的反覆試驗方法相比，這是一種創新且更有效的方法。為了展示TensorFlow作為深度學習的框架的方法相對於當前使用的實用程序的優勢，我們提供了八個業界電路的實驗數據。

With the increase in design complexity and test data volume, compressed tests together with on-chip test decompression hardware such as Embedded Deterministic Test (EDT) are widely used in industry to reduce test cost. One of the challenges of such Design-for-Test (DFT) technology is to determine a set of optimal parameters such as the number of scan chains, scan channels, power budget, etc. such that it can reach the highest test coverage with a minimum amount of test data volume whilst satisfying various other constraints. To achieve the optimal compression configuration quickly, in this thesis deep learning technology based on TensorFlow is explored to estimate the test coverage and the data volume for a design when employing EDT under a given set of circuit parameters. Based on the estimated data, the optimal test architecture is also predicted, yielding a more efficient approach compared to the currently used trial-and-error methods. To demonstrate the advantages of our deep learning approach over the currently used utility, we present experimental data for eight industrial designs.

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