本論文提出三個應用於逐漸趨近式類比至數位轉換器的電路設計技術，並且基於所提出的技術，實現一個使用九十奈米製程的單通道十位元每秒取樣一億二千萬次的非同步逐漸趨近式類比至數位轉換器。第一個技術為精簡組合電路時序控制，其簡化數位控制電路，節省其動態功率消耗，並去除傳統架構中浮動節點的漏電問題，降低漏電的功率消耗並使電路更加穩固。第二，我們提出非同步電路時脈改善技術，藉由同時將比較器輸出端電位的變化情況與電容陣列的上板電壓的穩定情形納入考量，依此來最小化數位電路的延遲時間，提升逐漸趨近式類比至數位轉換器的操作速度。第三，我們提出雜訊壓抑技術，在不消耗更多比較器功率的前提下，提升比較器的精確度。本設計使用台積電 90-nm UTM CMOS製程來實作晶片，其核心的電路面積為178.4 µm × 78.25 µm。從實際晶片量測結果顯示，此晶片在0.9伏特的電壓與每秒取樣一億二千萬次取樣的操作速度下，總消耗功率為0.81 mW，有效位元數為9.26 bits，每次資料轉換所消耗的能量為11 fJ，DNL與INL分別為+0.3/-0.69 LSB與+0.59/-0.55 LSB。

This thesis proposes three circuit design techniques for successive-approximation (SAR) analog-to-digital converters (ADCs). A single-channel 10-bit 180-MS/s asynchronous SAR ADC in 90-nm CMOS process was realized based on the proposed techniques.
First, the compact combinational timing control technique is proposed to simplify the digital control circuitry and to reduce the dynamic switching power consumption. The leakage problem from floating nodes is also removed to lower leakage power consumption and it makes the circuit more robust. Second, the enhanced asynchronous timing scheme is proposed to minimize the digital loop delay by taking both the output condition of the comparator and the DAC settling issue into consideration so that it can promote the operating speed of the SAR ADC. Third, the noise suppression technique is proposed to reduce the input-referred noise of the comparator without increasing the power consumption.
The proof-of-concept prototype was fabricated in TSMC 90-nm CMOS process. The core area is 178.4 µm × 78.25 µm. From measurement results, at 0.9 V supply voltage and 120-MS/s sampling rate, the total power consumption is 0.81 mW, and ENOB is 9.26 bits. It achieves a FoM of 11 fJ/conversion-step. The measured DNL and INL are +0.3/-0.69 LSB and +0.59/-0.55 LSB, respectively.

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