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研究生： 呂盈宏
Lu, Ying-Hung
論文名稱： 低功耗H.264條件化可調性可變長度解碼器
Low Power H.264 Context-Based Adaptive Variable Length Decoder
指導教授： 劉濱達
Liu, Bin-Da
楊家輝
Yang, Jar-Ferr
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2005
畢業學年度： 93
語文別： 英文
論文頁數： 97
中文關鍵詞： 低功率 、可變長度解碼 、影像壓縮
外文關鍵詞： vld, low-power, vlc, variable-length, adaptive, context-based, cavld, cavlc, H.264, avc, image compression
相關次數： 點閱：141  下載：1 
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    • 摘 要

    近幾年來，有許多影像壓縮標準系統皆應用在可攜式的系統之中，而這些可攜式的系統大部份皆經由電池提所需的能量。因此，對於影像壓縮系統而言，低功率的設計是必需的。對於廣播及視訊會議等應用而言，即時處理是另一個重要的議題。為了解決以上所提的兩個問題，總輸出量及功率消耗在此架構的設計過程中皆有加以考慮。在此篇論文中，我們提出了一個低功率消耗且可操作於高頻率之條件化可調性可變長度解碼器。此架構先改進H.264上解碼的程序，使得關鍵路徑之延遲縮短。另外，在此架構之中，我們使用表分解 (table partitioning) 及字首提前解碼 (prefix predecoding) 二種低功率的設計方法來減少解碼表中的功率消耗。此架構利用UMC 0.18m的製程技術合成，其合成的結果顯示，在時脈速度為200 MHz的情況下，所提出的條件化可調性可變長度解碼器能夠在4VGA (1280960) 的解析度下作即時處理。根據實驗結果，在跟沒有使用低功率設計的對照架構比較下，此架構可以減少約27%之功率消耗。

    abstract

    Recently, many video compression standards are applied to portable systems which are battery-powered. Thus, low power design is necessary for video compression systems. In many applications such as broadcasting and video conferencing, real-time processing is an important issue. To address the two issues described above, both the throughput and the power consumption should be taken into consideration in our design. In this thesis, a low-power context-based adaptive variable length decoder (CAVLD) in H.264/AVC with high decoding speed was implemented. In the proposed architecture, we first modify the decoding procedures defined in standard to reduce the critical path delay. Afterwards, both the two low power approaches called table partitioning and prefix predecoding are employed to reduce the power consumption in VLC tables. The proposed architecture is synthesized with UMC 0.18 m technology. The synthesized CAVLD could achieve real-time requirements for 4VGA (1280960) resolution at 200 MHz. In our simulation, the proposed architecture can reduce about 27% of power consumption compared to its counterpart without low power design.

    Table of Contents Table of Contents i Acknowledgement iv abstract vi List of Figures vii List of Tables ix Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization for the Thesis 5 Chapter 2 Basic Concepts of Video CODEC and Overview of H.264/AVC Video Coding Standard 6 2.1 Basic Concepts for Video Coding 6 2.2 Overview of Image/Video CODEC 10 2.2.1 Video Encoder 13 2.2.2 Video Decoder 15 2.3 Overview of H.264/AVC Video Coding Standard 15 2.3.1 Variable Block Size 17 2.3.2 Intra prediction 18 2.3.3 Integer Transform 19 2.3.4 In-Loop Deblocking Filter 21 2.3.5 Entropy Coding 23 Chapter 3 VLC-based Coding Scheme in H.264/AVC 24 3. 1 Introduction 24 3.2 Basic Hierarchy of Slice Data Syntax 26 3.3 Universal Variable Length Coding 28 3.4 Context-Based Adaptive Variable Length Coding 32 3.4.1 Encoding of Coeff_Token 34 3.4.2 Encoding of Trailing_Ones_Sign_flag 39 3.4.3 Encoding of Level_Prefix and Level_Suffix 39 3.4.5 Encoding of Run_Before 43 3.4.6 An Example of CAVLC Encoding Process 44 Chapter 4 Low Power CAVLC Architecture for H.264/AVC 49 4.1 Motivation 49 4.2 Real-time Requirements for Various Resolutions 50 4.3 Source of Power Consumption 52 4.4 Low Power Techniques for VLD 53 4.4.1 Table Partitioning 53 4.4.2 Prefix Predecoding 54 4.4.3 VLC Detector Optimization 55 4.5 Overview of Proposed Architecture 56 4.6 Input Buffer Architecture 57 4.7 Low Power FSM 59 4.8 Proposed Architecture of Coeff_Token 63 4.9 Proposed Architecture of Trailing_One_Sign_Flag 65 4.10 Proposed Architecture of Level 67 4.11 Proposed Architecture of Total_Zeros 72 4.12 Proposed Architecture of Run_before 73 Chapter 5 Simulation Results and Verification 75 5.1 Synthesis Results 75 5.2 Power Simulation Results 76 5.3 Verification 81 5.3.1 Verification Environment 81 5.3.2 RAM-Based Interface Connection 82 5.3.3 HW/SW Co-Simulation 85 5.4 Summary 88 Chapter 6 Conclusions and Future Work 89 6.1 Conclusions 89 6.2 Future Work 90 References 92

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