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研究生： 吳繼仁
Goh, Jih-Ren
論文名稱： 一個基於雙緣取樣式延遲鎖定迴路並操作於0.5 Gb/s至3 Gb/s之時脈與資料回復電路
A 0.5-to-3.0 Gb/s Dual Edge Sampling Delay-Locked Loop Based Clock and Data Recovery Circuit
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2014
畢業學年度： 102
語文別： 英文
論文頁數： 88
中文關鍵詞： 延遲鎖定迴路 、時脈與資料回復電路 、雙緣取樣 、時脈內嵌式螢幕介面
外文關鍵詞： DLL, CDR, dual-edge sampling, clock-embedded intra-panel interface
相關次數： 點閱：90  下載：5 
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    • 本論文提出了應用於時脈內嵌式螢幕介面，具有雙緣取樣特性的延遲鎖定迴路並操作於0.5 Gb/s至3 Gb/s之時脈與資料回復電路。結合所提出的雙緣取樣方式以及0.5 UI內嵌時脈編碼方式，本研究的延遲鎖定迴路可以節省4倍的延遲單元，達到節省硬體面積以及能量損耗的優勢。此外，透過適當的資料編碼方式以及使用本論文所提出的遮罩電路，可以讓電路的延遲容忍度提升2倍，提高了設計的穩健度。此時脈與資料回復電路晶片以台積電所提供的CMOS 180-nm製程進行設計與驗證。量測回復的時脈，所得到的上升緣及下降緣之抖動方均根值與資料周期比分別是3.6 % UI以及3.5 % UI。此晶片的核心電路面積是0.519*0.137 mm2以及其功率效率是1.43 mW/Gb/s。

    This thesis presents a 0.5-to-3.0 Gb/s dual edge sampling DLL-CDR for clock-embedded intra-panel interface applications. By combining the proposed dual edge sampling and half-UI embedded clock coding, the proposed DLL can save 4 times number of the required delay cells compared to the conventional DLL, which not only enhancing the power efficiency but also reducing silicon area. With a proper data coding method and the enhanced mask circuit, the delay tolerance is increased two-fold, making this CDR circuit more robust. This CDR circuit is designed and fabricated in TSMC 180-nm CMOS process. The measured root mean square (rms) jitter ratio of the rising edge and falling edge of the recovered clock at 3.0 Gb/s are 3.6 % UI and 3.5 % UI, respectively. The core area of the test chip is 0.519*0.137 mm2 and its power efficiency is 1.43 mW/Gb/s.

    ABSTRACT i Table of Contents iv List of Figures vi Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 8 Chapter 2 PLL, DLL, and CDR 9 2.1 Phase-Locked Loop (PLL) 9 2.1.1 Introduction to PLL 9 2.1.2 Qualitative Analysis on PLL 10 2.2 Delay-Locked Loop (DLL) 13 2.2.1 Introduction to DLL 13 2.2.2 Qualitative Analysis on DLL 14 2.2.3 DLL Design Issues 15 2.3 Delay-Locked Loop VS. Phase-Locked Loop 17 2.4 Clock and Data Recovery Circuit (CDR) 21 2.4.1 PLL-CDR and DLL-CDR 21 2.4.2 CDR Performance Metrics 22 2.4.3 CES-CDR 25 Chapter 3 The Proposed Clock-Embedded CDR 29 3.1 Specification 29 3.2 The Proposed Dual Edge Sampling 30 3.3 Architecture 33 3.4 System Design 36 3.5 Circuit Description 38 3.5.1 Voltage Controlled Delay Line (VCDL) 38 3.5.2 Bias Circuit (BIAS) 44 3.5.3 Charge Pump (CP) 46 3.5.4 Band Selector (BS) 47 3.5.5 Mask Circuit (MASK) 49 3.5.6 Coarse Lock Detector (CLD) 53 3.5.7 Reset Circuit 54 3.6 Layout and Floorplan 55 Chapter 4 Simulation and Measurement Results 58 4.1 DC Simulation 58 4.1.1 Bias Voltage 58 4.1.2 Charge Pump DC Current 60 4.2 Transient Simulation 61 4.3 Simulated Performance Results 66 4.4 Measurement Results 71 4.5 Comparison Table 85 Chapter 5 Conclusions and Future Work 86 Bibliography 87

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