本篇論文描述一個具有新設計技術之高速八位元互補金氧半快閃式類比數位轉換器。對於連續信號轉換的應用，無空轉時間之自動歸零技術是一個有效的方法來降低由於製程變動所產生的偏移誤差。再內插和平均化技術可以有效降低已經使用的前置放大器的面積和輸入負載。然而，要同時將無空轉時間之自動歸零與再內插和平均化技術實現於一高速低潛伏的快閃式類比數位轉換器是相當因難。在本設計中，新的自動歸零與再內插和電容平均化技術被提出來實現這個目標。一個開關式前置放大器被提出來避免傳統自動歸零所需之非重疊控制信號與消除高速自動歸零對輸入端造成的干擾。然而，相對於最近所發表之自動歸零之快閃式類比數位轉換器所需多相位時脈，所提出的技術有單一相位控制的優點並避免了同步問題。除此之外，所提出的技術使用再內插和電容平均化技術可以降低開關式前置放大器面積為原來的1/6倍。內插技術也被使用而來降低輸入負載、前置放大器數目以及差值非線性誤差。
　　這個類比數位轉換器實現是採用0.18μm，1P6M互補金氧半混合信號製程，面積為1.33×1.057mm2。量測結果證實此類比數位轉換器在輸入信號為1.484375MHz，在操作頻率為40MHz和250MHz時，具有44dB及38.9dB SNDR 的動態表現。整個晶片在1.8伏特的供應電壓下，消耗180mW的功率。

　This thesis presents a high-speed 8-bit CMOS flash ADC with new design techniques. Autozeroing technique without idle time is an effective way to suppress offset error due to process variation for the applications of continuous input conversion. Reinterpolation and averaging techniques can reduce the area and input capacitances of the used input preamplifiers practice the high-speed flash ADC efficiently. However, it is difficult to include autozeroing without idle time with reinterpolation and averaging techniques in a high-speed low-latency flash ADC. In the design, New Autozeroing with Reinterpolation and Capacitor Averaging technique is proposed to achieve the target. A Switching preamplifier is provided to avoid using non-overlap control signals required by conventional autozeroing ADCs and to eliminate the interference, caused by the high-speed autozeroing operation, at input nodes. However, this proposed technique has the merit of a single-phase control to avoid synchronous problems since multi-phase clocks are necessary for recent published flash ADCs with autozeroing. Besides, proposed technique with Reinterpolation and Capacitor Averaging techniques can reduce the area of the switching preamplifier 1/6. Interpolation technique also is used to reduce input loading, preamplifier number and differential nonlinearity (DNL) error in the ADC.
　The ADC is fabricated in 0.18μm 1P6M CMOS technology and occupies an area of 1.33x1.057mm2. The measurement results demonstrates that the ADC can digitize an input 1.484375MHz with 44dB and 38.9dB SNDR at 40Msample/s and 250Msample/s. The ADC consumes 180mW from 1.8V power supply.

[1]Koen Uyttenhove et al., "Design techniques and implementation of an 8-bit
200-MS/s interpolating/averaging CMOS A/D converter," IEEE J. Solid-State
Circuits, vol. 38, no. 3, pp. 483-494, Mar. 2003
[2]Kevin Kattmann and Jeff Barrow, "A Techniques for Reducing Differential
Non-Linearity Errors in Flash A/D Converters," in IEEE Int. Solid-State
Circuits Conf. (ISSCC), pp. 170-171, Feb. 1991.
[3]H. Kobayashi, J.L. White, and A.A. Abidi, “An active resistor network for
Gaussian filtering of images,” in IEEE J. Solid-State Circuits, vol. 26, no.
5, pp. 738-748, May. 1991.
[4]Behzad Razavi and Bruce A. Wooley, "Design Techniques for High-Speed,
High-Resolution Comparators," IEEE J. Solid-State Circuits, vol. 27, no. 12,
pp. 1916-1926, Dec. 1992.
[5]D.J Allstot, “ A Precision Variable Supply CMOS Comparator,” IEEE J.
Solid-State Circuits, vol. SC-17, pp. 1080-1087, Dec. 1982.
[6]J.Doernberg, P.R Gray, and D.A. Hodges, “A 10-Bit 5-Msample/s CMOS Two-Step
Flash ADC,” IEEE J. Solid-State Circuits, vol. SC-24, pp. 241-249, April.
1989.
[7]Sanroku Tsukamoto et al., "A CMOS 6-b, 200 MSample/s, 3 V-Supply A/D Converter
for a PRML Read Channel LSI," IEEE J. Solid-State Circuits, vol. 31, no. 11,
pp. 1831-1836, Nov. 1996.
[8]Kwangho Yoon, Sungkyung Park and Wonchan Kim, "A 6b 500MSample/s CMOS Flash ADC
with a Background Interpolated Auto-Zeroing Technique," in IEEE Int.
Solid-State Circuits Conf. (ISSCC), pp. 326-327, Feb. 1999.
[9]Jerry Lin, Baher Haroun, “An Embedded 0.8 V/480 uW 6B/22 MHz Flash ADC in
0.13-um Digital CMOS Process Using a Nonlinear Double Interpolation
Technique,”IEEE J. Solid-State Circuits, vol. 37, no. 12, pp. 1610-1617, Dec.
2002.
[10]B.Razavi, Principle of Data Conversion System Design, IEEE Press, New York,
1995.
[11]Y. T. Wang and B. Razavi, “An 8-Bit 150-MHz CMOS A/D Converter,” IEEE J.
Solid-State Circuits, vol. 35, no. 6, pp. 308-317, Mar. 2000.
[12]Krishnaswamy Nagaraji et al.,” A Dual-Mode 700-Msamples/s 6-bit
200-Msamples/s 7-bit A/D Converter in a 0.25-um Digital CMOS Process,” IEEE
J. Solid-State Circuits, vol. 35, no. 12, pp. 1760-1768, Dec. 2000.
[13]M.J.M Pelgrom, A.C.J. Duinmaijer, and A.P.G. Welbers, “Matching properties of
MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, pp. 1433-1440, Oct.
1989.
[14]Michael Choi and Asad A. Abidi, "A 6-b 1.3-Gsample/s A/D Converter in 0.35m
CMOS," IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1847-1858, Dec.
2001.
[15]Clemenz L. Portmann, and Teresa H.Y. Meng, ”Power-Efficient Metasbility Error
Reduction in CMOS Flash A/D Converters,” IEEE J. Solid-State Circuits, vol.
31, no. 8, pp. 1132-1140, Aug. 1996
[16]G. Van der Plas, W.D.aems, E.Lauwers, J.Vandenbussche, W.Verhaegen, G.Gielen,
and W.Sansen, ”Symbolic analysis of CMOS regenerative comparators,” in Proc.
Eur. Conf. Circuit Theory and Design, Aug. 1999, pp. 86-89. .
[17]K.Uyttenhove and M.Steyaert, “Speed-power-accuarcy tradeoff in high-speed
ADCs,” in Proc. IEEE Custom Integrated Circuits Conf, , May 2001, pp.
249-252.
[18]C.W. Mangelsdorf, “ A 400-MHz input flash converter with error correction,”
IEEE J. Solid-State Circuits, vol. 25, pp. 1825-1852, Dec. 2000.
[19]Tsutomu Wakimoto, Yukio Akazawa and Shinsuke Konka, “ Si Bipolar 2-GHz 6-Bit
Flash A/D Conversion LSI,” IEEE J. Solid-State Circuits, vol. 23, no. 6, pp.
1345-1350, Dec. 1988
[20]Declan Dalton etal., “ A 200-MSPS 6-Bit Flash ADC IN 0.6um CMOS,” IEEE J.
Solid-State Circuits, vol. 45, no. 11, pp. 1433-1444, Nov. 1998.
[21]Akira Matsuawa et al., “ A 6b 1GHz Dual-Parallel A/D Converter,” IEEE Int.
Solid-State Conf, pp. 174-175, Feb. 1991.
[22]M.Yotsuyanagi, H.Hasegawa, M.Yamaguchi, M.Ishida, K.Sone, ” A 2V, 10b,
20Msample/s, Mixed-Mode Subranging CMOS A/D Converter,”: IEEE J. Solid-State
Circuits, vol. 31, pp. 1533-1537, Dec. 1995.
[23]B.Razavi, B.Wooley, “ A 12-b 5-MSample/s Two-Step CMOS A/D Converter,” IEEE
J. Solid-State Circuits, vol. 27, no. 11, pp.1677-1678, Dec. 1992.
[24]Joey Doernberg, Paul R. Gray and David A. Hodges,” A 10-bit 5-Msample/s CMOS
Two-Step Flash ADC,” IEEE J. Solid-State Circuits, vol. 31, no. 2,
pp.241-249, Apr. 1989.
[25]Robert C. Taft and Maria Rosaria Tursi, "A 100-MS/s 8-b CMOS Subranging ADC
with Sustained Parametric Performance from 3.8V Down to 2.2V," IEEE J.
Solid-State Circuits, vol. 36, no. 3, pp. 331-338, Mar. 2001
[26]M.Choe, B. Song and K.Bacrania, “ An 8-b 100-Msample/s CMOS Pipelined Folding
ADC ,” IEEE J. Solid-State Circuits, vol. 36, no. 2, pp. 184-194, Feb. 2001