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研究生： 林恆瑤
Lin, Heng-Yao
論文名稱： H.264/AVC轉換域框內編解碼器之快速演算法及硬體架構設計
Fast Algorithms and VLSI Implementations of H.264/AVC Transform-Domain Intra Codec
指導教授： 劉濱達
Liu, Bin-Da
楊家輝
Yang, Jar-Ferr
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2009
畢業學年度： 97
語文別： 英文
論文頁數： 95
中文關鍵詞： H.264/AVC 、框內編碼 、轉換域 、快速演算法 、條件可調性非等長編碼
外文關鍵詞： context-based adaptive variable length coding (C, H.264/AVC, intra prediction, Transform domain, fast algorithm
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    • H.264/AVC為最新的數位視訊壓縮標準，藉由引進不同的編碼特點以獲得更高的壓縮效率。本論文完成於H.264/AVC視訊框內編解碼器之巨大區塊管線化硬體架構，來增進執行效能。轉換域之框內預測與內涵可適非等長編碼(CAVLC)之快速硬體架構為主要研究重點。
    針對演算法及硬體架構做最佳化設計，我們首先設計框內決策機制演算法。基於離散餘弦轉換的特性，將畫面內既有的資訊做轉換，進而從中偵測出目標方塊紋路的方向性來過濾不必要的預測方向。利用絕對和之整數離散餘弦轉換誤差法(SAITD)的特性，在整個框內編碼的效能可獲保持下，計算速度得到相當大的改進。與現今的相關研究比較，本演算法可減少約60%的編碼時間，而影像品質均有較優的表現。在硬體設計上，此演算法可完全融入框內編碼器中，並非只是單純的前置處理單元。至於最佳預測殘值，則可以直接由預測過程中得到，而不必重新計算。
    接著，我們分析內涵可適非等長編碼(CAVLC)之關鍵路徑，透過提前執行條件偵測，來縮短關鍵路徑之延遲，並將內涵可適非等長編碼電路分割成兩部份，進行管線化架構設計，以提升整體執行效能。我們使用表分解(table partitioning)及字首提前解碼(prefix predecoding)二種低功率的設計方法，來減少解碼表中不必要的功率消耗。並使用結合解碼表及單一輸出緩衝器之方法，在不影響解碼效能下更進一步減少硬體面積及功率消耗。跟傳統H.264解碼效能相比之結果，本論文所提出的架構能減少約40%功率消耗，並提升三倍解碼速度。
    最後，本H.264/AVC視訊框內編解碼器經TSMC 0.18 μm製程技術合成後，最高操作頻率達100 MHz，可即時處理每秒30張16 SIF (1408×960)解析度的影像。

    H.264/AVC is the latest digital video coding standard that achieves very high data compression by using several new coding features. In this dissertation, a highly efficient VLSI architecture with macroblock pipeline structure is proposed to increase the coding speed for intra frame codec in H.264/AVC. The major researches include fast implementations of transform-based intra prediction and context adaptive variable length coder (CAVLC).
    For optimized algorithm and architecture design in intra prediction, a fast mode decision algorithm is represented based on inherent features of discrete cosine transform (DCT). The primary texture direction of the target block can be determined by using the transformed coefficients of the block. Only a few candidate modes are chosen for the cost calculation, which is based on the error model in the sum of absolute integer-transformed differences (SAITD). Experimental results show that the proposed intra prediction algorithm has lower Peak Signal to Noise Ratio (PSNR) degradation and bit-rate increment with the reduction of the coding time by 60% compared to other recent designs. For hardware implementation, the proposed intra prediction algorithm is integrated into intra prediction procedure rather than being a preprocessing units. The residual blocks of the best prediction mode can be obtained directly after the cost generator without re-computing in the intra prediction procedure.
    In the entropy codec module, the critical path in the CAVLC decoder is first analyzed and then reduced by forwarding the adaptive detection for succeeding symbols. With a shortened critical path, the CAVLC architecture is further divided into two segments, which can be easily implemented by a pipeline structure. Consequently, the overall performance is effectively improved. In the hardware implementation, we suggested two efficient approaches, table partitioning and prefix predecoding, to reduce the unnecessary power consumption in decoding the look up table (LUT) of VLC codes. Moreover, a combined LUT and single output buffer have been adopted to further reduce the area as well as power consumption without affecting the decoding performance. Experimental results show that the proposed architecture surpassing other recent designs can approximately reduce power consumption by 40% and achieve three times decoding speed in comparison to the original decoding procedure suggested in the H.264 standard.
    Finally, the H.264/AVC transform-based intra codec with TSMC 0.18 μm CMOS technology is realized, where the maximum operation frequency can achieve at 100 MHz, which can easily support the real-time requirements for video resolutions up to the 16 SIF (1408×960) at 30 frames/sec video format.

    Abstract i List of Tables ix List of Figures x CHAPTER 1 Introduction 1 1.1 Background and Motivation 1 1.2 Organization of the Dissertation 5 CHAPTER 2 Basic Concepts of the H.264/AVC Intra Codec 6 2.1 Overview of H.264/AVC Standard 6 2.2 Intra Prediction Modes 8 2.3 Mode Decision 9 2.4 Transform and Quantization 10 2.5 Entropy Coding 13 CHAPTER 3 Transform-based Intra Mode Decision Algorithm 16 3.1 Characteristic of Transform Function 16 3.2 Luma 4×4 Intra Prediction 18 3.2.1 Detection of DC mode 20 3.2.2 Detection of AC modes 21 3.2.3 Most probable mode 23 3.2.4 Summary 24 3.3 Luma 16×16 Intra Prediction 25 3.4 Chroma 8×8 Intra Prediction 27 3.5 SAITD Technique 29 3.6 Simulation Results 30 3.6.1 Threshold value determination 31 3.6.2 RDO enabled 33 3.6.3 RDO disabled 39 CHAPTER 4 Hardware-Oriented CAVLC Decoder Algorithm Optimization 42 4.1 Real-Time Requirement 43 4.2 Original Level Decoding Process 45 4.3 Critical Path Improvement in Decoding Level 48 4.3.1 Normal mode with suffixLength > 0 49 4.3.2 Normal mode with suffixLength = 0 51 4.3.3 Escape_code mode 52 4.3.4 TrailingOnes mode 52 4.3.5 Summary 53 4.4 Throughput Improvement in Decoding Sign of T1s 54 4.5 Simulation Results 55 CHAPTER 5 VLSI Architecture Design of Transform-based Intra Codec 57 5.1 Transform-based Intra Prediction Architecture 58 5.1.1 Integer transform 59 5.1.2 Prediction generator 63 5.1.3 Cost generation and mode decision 67 5.1.4 Reconstruction loop 67 5.1.5 Register array 69 5.1.6 System controller 69 5.1.7 Timing schedule 73 5.2 CAVLC Encoder 74 5.3 CAVLC Decoder 75 5.3.1 Low power LUTs decoders 75 5.3.2 Combined LUTs decoder 78 5.3.3 Output buffer 80 5.3.4 Power consumption analysis 82 5.4 Synthesis Results and Comparisons 83 CHAPTER 6 Conclusions and Future Work 85 6.1 Conclusions 85 6.2 Future Work 87 References 89 Publication List 94

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