| 研究生: |
許嘉麟 Hsu, Chia-Ling |
|---|---|
| 論文名稱: |
氧化鋅奈米線電晶體元件之製作與分析 Fabrication and Characterization of ZnO Nanowire Transistors |
| 指導教授: |
洪昭南
Hong, Chau-Nan Franklin |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 化學工程學系 Department of Chemical Engineering |
| 論文出版年: | 2008 |
| 畢業學年度: | 96 |
| 語文別: | 英文 |
| 論文頁數: | 117 |
| 外文關鍵詞: | Transistor, ZnO, Nanowire |
| 相關次數: | 點閱:40 下載:0 |
| 分享至: |
| 查詢本校圖書館目錄 查詢臺灣博碩士論文知識加值系統 勘誤回報 |
Firstly, we grew ZnO nanowires via vapor transport method with the high-temperature furnace, and highly uniform and densely packed ZnO nanowire arrays were obtained. A series of material measurements have been conducted from the aspects of morphological, structural, optical, and chemical properties. According to TEM and XRD analyses, the obtained ZnO nanowires grew along the direction of (c-axis) without obvious defects and belonged to hexagonal wurtzite structure with lattice parameters of a=0.325 nm and c=0.521 nm. In optical analyses, PL and CL, indicated that the band gap of as-grown nanowires is about 3.27 eV and helped us to realize the surface states which were originated from oxygen vacancies. Raman spectra reveal the crystallinity of nanowires, while ESCA and EDS analyses confirm the chemical compositions. Besides the material characterizations, we also discussed the influence of zinc evaporated volume on the growth conditions toward nanowire properties. The synthesized ZnO nanowire arrays were also used to prepare super-hydrophobic surface, and the importance of the micro-nano binary structure has been illustrated.
In the second part, we demonstrated a methodology to arrange and transfer vertically aligned nanowires from the growth substrate to acceptor target via contact printing process. We successfully obtained oriented assembly of nanowires with the uses of PMMA and PDMS films by the roller machine. Through applying the demonstrated nanowire arrangement method, we fabricated multiple ZnO nanowire transistors with excellent electrical performances. Through calculations for the electrical properties, the values of threshold voltage, carrier concentration, transconductance, mobility, subthreshold swing, and on/off ratio are 2.07 V, 1.64 × 1016 cm-3, 1.70 × 10-7 S, 7.39 × 101 cm2V-1s-1, 330 mV/decade, and 1 × 106, respectively. We also fabricated transistors with anomalous electrical properties by using the nanowires grown in different batch. To investigate the origin of this difference, we correlated material characterizations with electrical properties. Finally, we found an underlying failure that might present in the device fabrication process.
In the final section, we developed a novel method to fabricate nanowire transistors by combining the working principles of DEP and imprinting pattering. We successfully arranged nanowires to cross between the etched source-drain electrodes mold, and used the interdigitated mold to fabricate PMMA patterns with great conformity. However, the DEP step for the nanowire alignment would impose a problem in the subsequent imprinting process. Though the concrete transistor has not been demonstrated yet, we proposed the main process challenge that might be met in following parameter adjustments.
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