| 研究生: |
羅聖心 Lo, Sheng-Hsin |
|---|---|
| 論文名稱: |
IPsec資料庫查詢單元之軟硬體協同設計 Hardware and Software Co-design of IPsec Database Query |
| 指導教授: |
陳中和
Chen, Chung-Ho |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2012 |
| 畢業學年度: | 100 |
| 語文別: | 中文 |
| 論文頁數: | 69 |
| 中文關鍵詞: | 資料庫查詢 、電子系統層級設計 、IPsec 、軟硬體協同設計 |
| 外文關鍵詞: | database query, electronic system level design, IPsec, software/hardware co-design |
| 相關次數: | 點閱:105 下載:2 |
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隨著網路普及,人們對網路隱密性也越來越重視。因此IETF提出了IP Security (IPsec) 網路傳輸協定,在不更改目前網路架構下,提供加解密與認證的服務。開啟IPsec後,每個傳送或接收的封包皆須進入IPsec資料庫作查詢,當網路速度越來越快,用軟體搜尋便無法達到需求。
本篇論文中,我們針對IPsec資料庫搜尋流程分析,提出了針對SPD與SAD特性設計之軟體演算法,並對其資料結構與搜尋流程作了詳盡的介紹與分析。為了達到網路加速的效果,我們以硬體加速的方式配合軟體搜尋,在此我們提出了Scratchpad Memory、Hardware Cache與Software Cache三種硬體架構。
我們在ESL設計平台上,以SystemC語言實現我們的設計,配合ARM處理器,在Platform Architect上實現,並且提供一個On-line Verification的環境,與真實Linux進行驗證。Software Cache在對SP Policy具有256個Policy的情況下,可提升83.54%的效能增益,Hardware Cache可以提升85.89%的效能增進,Scratchpad Memory則可達到83.87%的效能增進,Software Cache既可擁有近似Hardware Cache的效能,且不必消耗太多硬體設計成本。
With the popularity of the Internet, confidentiality requirements for the Internet have become more critical. The IEFT has proposed IP security to provide services of encryption/decryption and authentication without changing current network architecture. After enabling IPsec, every transmitted or received packet must query the IPsec database. As the speed of network increases, software searching of the IPsec database may become the critical path.
The purpose of this thesis is to describe and analyze a database structure as well as its querying flow for IPsec and propose a database searching algorithm for Security Policy Database and Security Association Database. In order to accelerate the speed of IPsec Database querying, the application of hardware acceleration together with software searching is used. We evaluate three designs: scratchpad memory, hardware cache and software cache.
We use SystemC language to implement our design in ESL virtual platform with the ARM processor. The design proposed in this work is implemented in Platform Architect and provides an on-line verification environment. Compare to software searching with 256 security policies, the software cache can reduce 83.54% querying time, hardware cache can reduce 85.89% querying time and scratchpad memory can reduce 83.87% querying time. We found that the efficiency of software cache is nearly equal to hardware cache and consumes less cost.
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