由於現代IC設計複雜度增加和時脈的提升，晶片測試已經為IC產業不可或缺的一個部分。為確保高效能的晶片運作在正確的時脈，小延遲缺陷測試現已廣泛的被運用在工業上。許多的自動測試圖樣產生工具透過擷取電路的時間資訊，進而選擇較長的路徑去激發小延遲缺陷，以得到更高品質的測試資料集。然而這些方法皆有測試資料生成時間過長，以及大量增加測試資料的缺點。
在這篇論文中，我們提出了一個不同於以往的小延遲缺陷測試資料生成技術，此技術是基於透過擷取電路中長路徑的共同部分，並使用自定義的錯誤模型去增加額外的條件在這些擷取出來的路徑上，從而影響自動測試圖樣產生工具傳遞小延遲缺陷經過這些長路徑。我們的方法可以達到更佳壓縮的測試資料以及較高的延遲測試涵蓋率，與常見的時間感知自動測試圖樣產生工具相比，我們提出的方法能降低19.2%的測試資料數以及增加0.74%的延遲測試涵蓋率。

To ensure the quality of high-performance VLSI chips, small delay defects (SDDs) are widely considered in the industry. Several ATPG tools have been developed to deal with these defects, with timing information employed to help select long paths that are more sensitive to small delays and hence high-quality tests can be generated. However, these methods usually require long test generation time and may result in large pattern count.
In this thesis, we propose a novel test generation method for SDDs based on a common path stem concept. By extracting the common path stems of those long paths in a circuit, one can use the user-defined fault model (UDFM) to set some conditions on the path stems and thus force the fault effects of SDDs to propagate through long paths, such that a compact pattern set can be generated and high delay test coverage (DTC) can be achieved for SDDs. Compared with the well-known timing-aware ATPG, our proposed method can reduce 19.2% pattern count and increase 0.74% DTC on average for ISCAS89 and IWLS05 benchmark circuits.

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