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研究生：	曾志強 Tzeng, Chih-Chiang
論文名稱：	最佳化功率/面積之介面電路合成 Optimal Power/Area Synthesis of Interface Circuits
指導教授：	賴源泰 Lai, Yen-Tai
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2006
畢業學年度：	94
語文別：	英文
論文頁數：	44
中文關鍵詞：	啟發式演算法、介面電路
外文關鍵詞：	interface circuit, heuristic algorithm
相關次數：	點閱：92 下載：2
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　　在一個SoC設計當中，其中一個最重要的議題就是矽智產(IP)之間的I/O介面整合問題。但是隨著半導體製成的演進，系統設計變得更複雜，故以IP為基礎的設計被期望用來降低設計時所付出的努力跟時間。通常大部分的IP均為不同賣方所提供，所以其I/O介面特性也均為不同。故整合IP之間的介面電路是非常消耗時間的且容易產生錯誤的，因此I/O介面電路的產生跟驗證對於事先設計好的IP是相當重要的。
　　在本篇論文當中，我們針對I/O介面電路當中為直接連線的部份提出一個介面合成演算法，演算法的輸入為一個權重二分圖來表示IP之間的I/O介面電路，並經由此演算法來決定如何整合。我們的啟發式演算法(heuristic algorithm)主要包含兩大部份：在第一個部份中，我們將得到權重二分圖中最低功率解。在第二的部份之前，先取得使用者所定義的功率上限，我們在此上限內將得到最佳輸出腳個數解。實驗的結果顯示我們演算法具有效率。

　　In a Soc design, the I/O interface of Intellectual Property (IP) blocks is one of the most important issues. But as semiconductor technology advances, system design become complex, IP-based design is expected reduce design effort and time-to-market. Since most IP’s are provided by different vendors, so they have different I/O interface characteristics. The design of interface circuitry for the IP’s is a time consuming and error-prone process. Therefore, I/O interface generation and verification for these pre-designed IP are very important.
　　In this thesis we propose an interface synthesis algorithm for direct connection of IP blocks. This algorithm accepts the weighted bipartite graph as input file represented I/O interface circuits of IP’s such that IP’s can be integrated. Our Algorithm consists of two phases: 1) Power Optimization Phase, which finds the optimal power solution of this weighted bipartite graph. 2) Output Pin Reduction Phase, which according to the given upper bound power, find a feasible solution which is smaller than or equal to the upper bound power and has the minimum output pin number. Experiment results demonstrate the effectiveness of our algorithm.

Abstract
Acknowledge
Contents
List of Figures
List of Tables
Chapter 1 Introduction 
 1.1 System-on-a-Chip Era..................................................................1 
 1.2 Interface Circuit Design...............................................................2 
 1.3 Related Works.............................................................................4 
 1.4 Organization of the Thesis...........................................................6 
Chapter 2 Problem Statement 
 2.1 Timing Diagram..........................................................................7 
 2.2 Timed Signal Transition Graph..................................................12 
 2.3 Modeling...................................................................................13 
 2.4 Merging Operation and Verify Timing......................................15
 2.5 Building the Interface Graph and Intersection Graph................17 
Chapter 3 Interface Synthesis for Direct Connection 
 3.1 Problem Formulation................................................................19
 3.2 Trade-Off Problem....................................................................21 
 3.3 Heuristic Algorithm..................................................................23 
  3.3.1 Power Optimization Phase.....................................................24 
  3.3.2 Reduce Output Pin Phase......................................................26 
  3.3.3 Example of Heuristic Algorithm............................................28
Chapter 4 Interface Synthesis for Logic Gate Connection 
 4.1 Problem Formulation................................................................31 
 4.2 Discrete Representation of a Waveform...................................32
 4.3 Signal Composition..................................................................34
 4.4 Heuristic Algorithm..................................................................35 
 4.5 Summary..................................................................................37
Chapter 5 Experimental Results 
Chapter 6 Conclusions and Future Works 
References
                                    

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校內：2007-07-25公開
校外：2007-07-25公開

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