神經網路已被廣泛應用在各種領域，傳統神經網路訓練需要大量有標籤訓練集，然而有標籤訓練集需要人工為數據進行標記，造成極高的成本，因此不需要人類介入，能夠自主學習的自主式神經網路成為未來發展的趨勢。本文結合對偶學習與生成對抗式網路，提出一種新的生成對抗式對偶學習方法，只需要無標籤訓練集即可進行訓練，達到類自主式學習之效果。由於神經網路之構成包含RNN、CNN等多種不同架構，且往往需要大量運算，因此需要一個通用的加速器來加速計算，本文提出一個通用可重構加速器，其支援多種data flow，且藉由可重構特性，能夠將硬體資源分割以平行執行多個任務，提升資源利用率。目前沒有方法能夠自動化的找到最佳的可重構配置，因此必須由人工決定如何分割PE Array，為了快速驗證不同神經網路在不同大小形狀的PE Array上執行的速度用以決定適合的可重構配置，本文提出通用型可重構硬體架構模擬器，此模擬器根據前述的硬體架構設計，模擬特定data flow下，資料在Buffer和PE之間的傳遞，並在PE內做乘加運算。模擬器的輸入參數化，可以任意調整不同的神經網路參數和PE Array，做cycle accurate的模擬。我們模擬了不同大小的PE Array和不同平行加速方法的執行時間。

Neural networks have been widely used in various fields. Traditional neural network training requires a large number of labeled training sets. However, labeled training sets need to manually label the data, resulting in extremely high costs, so it does not require human intervention and can learn independently the autonomous neural network has become the trend of future development. This paper combines dual learning and generative adversarial networks, and proposes a new generative adversarial dual learning method, which only needs unlabeled training set to be trained to achieve the effect of autonomous-like learning. Since the composition of neural networks includes a variety of different architectures such as RNN and CNN, and often requires a lot of calculations, a general accelerator is needed to accelerate calculations. This paper proposes a general reconfigurable accelerator that supports multiple data flows and can be the reconfigurable feature can divide hardware resources to execute multiple tasks in parallel and improve resource utilization. At present, there is no method to automatically find the best reconfigurable configuration. Therefore, it is necessary to manually decide how to divide the PE Array. In order to quickly verify the execution speed of different neural networks on PE Arrays of different sizes and shapes, determine the appropriate reconfigurable configuration. This paper proposes a general-purpose reconfigurable hardware architecture simulator. This simulator simulates the transfer of data between Buffer and PE under a specific data flow based on the aforementioned hardware architecture design, and performs multiplication and addition operations in PE. The inputs of the simulator are parameterizing, it can adjust different neural network parameters and PE Array arbitrarily to make cycle accurate simulation. We simulated the execution time of different sizes of PE Array and different parallel acceleration methods.

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