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研究生： 徐浩麟
Tsui, Hou-lon
論文名稱： 無前端取樣保存放大器之3-V、28-mW、十位元、20-MS/s管線式類比數位轉換器
A 3-V 28-mW 10-bit 20-MSample/s Pipeline ADC Without Using a Front-End Sample-and-Hold Amplifier
指導教授： 魏嘉玲
Wei, Chia-ling
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 67
中文關鍵詞： 管線 、取樣保持放大器 、啟動開關 、類比數位轉換器
外文關鍵詞： sample-and-hold amplifier, pipeline, Analog-to-digital converter, bootstrapping switches
相關次數： 點閱：83  下載：2 
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    • 本碩論係使用台灣積體電路公司(TSMC) 2P4M 0.35-μm CMOS製程，提出一個十位元、每秒二千萬次取樣之低功率管線式類比數位轉換器。為避免使用取樣保存放大器，因此轉換器的第一級採用新的架構；並配合寛擺幅之增益提高摺疊疊接放大器以降低功率消耗。除了利用回授電容切換技術，作為電容不匹配之補償外，轉換器亦採用啟動關關來取樣輸入訊號；此電路之優點為輸入訊號頻率相當於轉換器取樣速度。根據模擬結果，轉換器之差分非線性度及積分非線性度分別為 0.31-LSB 和 0.45-LSB。當輸入訊號達尼奎斯特頻率(10-MHz)時，其有效位元亦高於9.5位元。此轉換器晶片包含電壓參考電路，於3-V之操作電壓下，消耗功率及核心面積為28-mW和0.76-mm2。

    This thesis describes a low power 10-bit 20-MS/s pipeline analog-to-digital converter (ADC) implemented in TSMC double-poly four-metal 0.35-μm CMOS technology. A new configuration at the first pipeline stage avoids using a dedicated sample-and-hold amplifier (SHA). The ADC employs a wide-swing, gain-boosted folded-cascode amplifier to further reduce power consumption. In addition to compensating for capacitor mismatch with a commutated feedback capacitor switching (CFCS) technique, the ADC introduces gate-bootstrapping switches to sample inputs with frequencies comparable to its sampling rate. The simulated differential and integral nonlinearity of the ADC are within 0.31 least significant bit (LSB) and 0.45-LSB respectively at full sampling rate. It exhibits higher than 9.5 effective number of bits (ENOB) for an input frequency at Nyquist (fin = 10-MHz). The ADC core consumes 28-mW including the on-chip voltage reference from a 3-V supply and occupies an area of 0.76-mm2.

    Chapter 1. Introduction 1 1.1. Motivation 1 1.2. Contributions 2 1.3. Thesis Organization 3 Chapter 2. Overview of the Pipeline ADC Architecture 4 2.1. Introduction 4 2.2. Overview 4 2.2.1 Redundant Sign Bit (RSD) 6 2.3. Critical Building Blocks in the Pipeline ADC 8 2.3.1 Sub-Analog-to-Digital Converter (sub-ADC) 8 2.3.2 Multiplying Digital-to-Analog Converter (MDAC) 9 2.3.3 Digital Error Correction Logic 11 2.3.4 Reference Voltage Generator 13 2.3.5 Clock Generator 14 2.4 Design Constraints of Pipeline ADC 15 2.4.1 Capacitor Sizing and Scaling 15 2.4.2 Open Loop DC-Gain of the Amplifier 16 2.4.3 Settling of the Amplifier 17 Chapter 3. System and Circuit Architecture Design 21 3.1. Introduction 21 3.2. Sample-and-Hold Removal 21 3.2.1. Architecture Description 22 3.3. Commutated Feedback Capacitor Switching Technique 24 3.3.1. Motivation 24 3.3.2. Principle of Operation 25 3.4. A High speed MOS Switch 29 3.4.1. Sampling Nonlinearity 30 3.4.2. Bootstrap Operation 31 3.4.3. Proposed Bootstrap Technique 32 3.4.4. Design Guidelines 33 Chapter 4. Design Implementation 36 4.1. ADC Architecture 36 4.2. On-Chip Voltage Reference 37 4.2.1 Temperature Dependence of Emitter Base Voltage 37 4.2.2 Proposed Curvature-Compensated CMOS Bandgap Reference 38 4.2.3 Vcm Buffer 40 4.2.4 Reference Buffer 41 4.3. Tunable Current Reference and Bias Circuit 44 4.3.1 Constant Current Source 44 4.3.2 Bias Circuit 44 4.4. Clock Generator 46 4.5. MDAC 47 4.6. Sub-ADC/DAC 47 4.7. Dynamic Comparator 48 4.8. Opamp 50 4.8.1 Gain Boosting Introduction 50 4.8.2 Full Amplifier Architecture 52 4.8.3 Boosting Amplifier Design 52 4.9. Stage scaling 54 Chapter 5. Experimental Prototype and Simulation Results 56 5.1. Prototype 56 5.1.1 Layout Floor Plan 56 5.1.2 On-chip VDD Filter 56 5.2 Simulation Result 58 5.2.1 Dynamic Linearity and Noise Performance 58 5.2.2 Static Linearity 58 5.2.2 Summary 60 Chapter 6. Conclusion 63 Bibliography 65

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