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研究生：	范文騰 Fan, Wen-Teng
論文名稱：	具有數位頻率追蹤機制的鎖相迴路式時脈產生器 A PLL-Based Clock Generator with Digital Frequency Tracking Scheme
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	78
中文關鍵詞：	時脈產生器、鎖相迴路
外文關鍵詞：	clock generator, phase-locked loop
相關次數：	點閱：104 下載：8
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　　本論文主題在於設計並改良一個依據鎖相迴路原理的時脈產生器。這個時脈產生器的應用範圍是DVD/Audio系統，其輸入參考頻率為該系統的主要時脈(Master Clock)，範圍為4.096MHz至73.728MHz，對應於不同的輸入頻率，此產生器做一倍、二倍或四倍的倍頻動作，輸出範圍為16.384MHz至73.728MHz。本論文中，我們設計了兩個鎖相迴路式時脈產生器。

　　在鎖相迴路系統中，輸入參考信號對於輸出信號的影響為低通，而內部壓控振盪器對於輸出信號的影響為高通。故當參考信號源為理想的晶體振盪器時，即壓控振盪器產生之雜訊較嚴重時，迴路頻寬越大越好。若當參考信號為較不理想的情況下，則頻寬越小越好。在第一個鎖相迴路中，我們針對不同的參考信號源，設計了兩個不同的迴路頻寬，以分別應用於不同的情況。此外，迴路頻寬亦會影響鎖定時間，頻寬越小鎖定時間越長。在此，我們利用一個五個狀態的相位頻率偵測器來改善這個缺點，讓此鎖相迴路在兩個不同的頻寬下，鎖定時間是相近的。

　　第二個鎖相迴路使用雙迴路架構，一為數位頻率追蹤迴路，一為傳統鎖相迴路。當電路啟動時，數位頻率追蹤迴路會先將輸出頻率校正到一定範圍內，即傳統鎖相迴路可修正的範圍內，再透過此迴路將頻率及相位修正，達到相位鎖定的狀態。採用此雙迴路架構，可以減小壓控振盪器的增益，減小輸出信號對控制電壓的敏感度；藉由降低壓控振盪器的增益亦可以減小迴路濾波器中所需要的電容值，達到降低成本的效果。

　　此二個鎖相迴路均採用0.35um 2P4M 互補式金氧半混合信號製程成功地實現，第一個晶片的面積為0.41mm2，在3.3伏特的供應電壓下，功率消耗為13.2mW。第二個晶片面積為0.35mm2，18.4mW。

　　The goal of this thesis is to design and improve a PLL-based clock generator, a clock generator for DVD/Audio system. The system master clock(MCLK) is the input reference signal of the clock generator and its frequency range is from 4.096MHz to 73.728MHz. Besides, the clock generator has corresponding frequency multiplication such as four, two and one, according to the different input frequency band. The output frequency range is from 16.384MHz to 73.728MHz. In this thesis, two PLL-based clock generators are designed.

　　According to PLL design technique, we could find that the loop bandwidth of PLL would affect the jitter performance. To minimize the jitter due to external reference clock, the loop bandwidth of PLL should be made as narrow as possible. Conversely, to suppress the jitter due to internal voltage controlled oscillator, the loop bandwidth should be made as wide as possible. In the first design, there are a wide and a narrow loop bandwidth for different reference clock. In addition, the narrow loop bandwidth would cause the longer lock time than the wide one. A five-state phase/frequency detector is adopted to solve this problem and make the lock time in wide and narrow loop bandwidth almost the same. The second design is a dual loop phase-locked loop. One is the digital frequency tracking loop and the other is the fine tune phase-locked loop. After the digital frequency tracking loop finish the frequency tracking scheme, fine tune PLL continue to make the phase lock. Because the fine tune PLL has a lower VCO gain, the output phase jitter due to control voltage would be suppressed. Besides, the lower VCO gain would decrease the loop capacitor to lower the cost.

　　These two chips are both successfully implemented in 0.35um 2P4M CMOS mixed-mode technology. The two chips occupy an area of 0.41mm2 and 0.35mm2 and consume 13.2mW and 18.4mW from 3.3V power supply respectively.

Chapter 1 Introduction                                                 
1  Background  .....................................................  1
2  Motivation  .....................................................  2
3  Thesis Organization  ............................................  3

Chapter 2   Fundamentals of Phase-Locked Loop                              
1  Principle of operation  .........................................  5
2  Building Blocks of Phase-Locked Loop  ...........................  7
2.1  Phase/Frequency Detector  ................................  7
2.2  Voltage Controlled Oscillator  ...........................  9
2.3  Charge Pump and Loop Filter  ............................. 13
3  Loop Analysis and Behavior Simulation  .......................... 14

Chapter 3   A PLL-Based Clock Generator Using Modified Tri-State Phase   
            Frequency Detector
1  Specification  .................................................. 19
2  Architecture Design  ............................................ 21
2.1  Frequency Multiplication  ................................ 21
2.2  Loop Bandwidth  .......................................... 23
2.3  Modified Tri-State Phase Frequency Detector   ............ 25
2.4  Whole Architecture and Behavior Simulation   ............. 29
3  Circuit Implementation  ......................................... 31
3.1  Voltage Controlled Oscillator  ........................... 31
3.2  Charge Pump and Loop Filter  ............................. 35
3.3  Modified Tri-State Phase Frequency Detector  ............. 37
3.4  Divider  ................................................. 38
3.5  Control Unit  ............................................ 39
4  System Simulation Result  ....................................... 40
5  Floor Plan and Layout Consideration  ............................ 43
6  Measurement Consideration and Experimental Result  .............. 45
7  Summary  ........................................................ 49

Chapter 4   A PLL-Based Clock Generator with Digital Frequency Tracking 
            Scheme
1  Introduction  ................................................... 51
2  System Design Consideration  .................................... 52
2.1  Noise Analysis  .......................................... 52
2.2  Architecture Design  ..................................... 54
2.3  System Behavior Simulation  .............................. 56
3  Circuit implementation  ......................................... 59
3.1  Digital Frequency Tracking Loop  ......................... 59
            4.3.1.1  Control Voltage Generator ....................... 60
            4.3.1.2  Frequency Detector  ............................. 64
            4.3.1.3  Digital Coarse Tuning Circuit  .................. 65
3.2  Conventional Phase-Locked Loop  .......................... 65
4  System Simulation Result  ....................................... 66
5  Layout and Measurement  ......................................... 68
6  Summary  ........................................................ 73

Chapter 5   Conclusions
1  Conclusions  .................................................... 75

Reference  ........................................................... 77

                                    

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校內：2005-07-16公開
校外：2005-07-16公開

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