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研究生：	丁滎隍 Ting, Ying-Huang
論文名稱：	H.264視訊解碼器之外部與內部補償架構設計 Inter and Intra Compensation Architecture Designs for H.264 Video Decoders
指導教授：	劉濱達 Liu, Bin-Da 楊家輝 Yang, Jar-Ferr
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2005
畢業學年度：	93
語文別：	英文
論文頁數：	60
中文關鍵詞：	解碼器、內部與外部補償
外文關鍵詞：	intra, inter, H.264
相關次數：	點閱：69 下載：1
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　　本篇論文的主旨在於提出適用於H.264/AVC的內部與外部補償架構設計。內部預測值產生器每個時脈週期可以產生十六個內部預測值；在外部分數位置插值器方面，我們提出了兩種架構——管線化架構以及多時脈週期架構。本設計的架構使用UMC 0.18m的製程技術合成，並使用Verilog-XL進行模擬。內部預測值產生器的合成結果顯示，在83.3 MHz的時脈速度之下，此架構可以達到1333.33 M samples/sec的處理速度。管線化外部分數位置插值器的合成結果顯示，在100 MHz的時派速度之下，此架構可以達到1600 M samples/sec的處理速度。多時脈週期外部分數位置插值器的合成結果顯示，當最差的情況發生時，在66.67 MHz的時脈速度之下，此架構可以達到62.75 M samples/sec的處理速度。與720p HD (1280×720)的視訊規格相比較，本設計可以達到即時處理的要求。

　　In this thesis we propose the architectures of intra prediction sample generator and inter fractional sample interpolator for H.264/AVC. For intra prediction sample generator, our architecture can generate 4×4 intra prediction samples per clock cycle. For inter fractional sample interpolator, we propose two architectures--pipelined and multi-cycle. Our designs are synthesized with UMC 0.18 m technology and simulated with Verilog-XL. We further verify the functionality of the proposed architectures on the ARM development platform to carry out the hardware/software co-simulation. The synthesized intra prediction sample generator can process 1333.33 M samples/sec at 83.33 MHz. The synthesized pipelined inter fractional sample interpolator can process 1600 M samples/sec at 100 MHz. The synthesized multi-cycle inter fractional sample interpolator can process 62.75 M samples/sec at 66.67 MHz when the worst case occurs. The simulation results show that all of our designs can meet the requirement of real-time processing for 720p HD (1280×720) video format.

Table of Contents	i
Acknowledgement	iii
Abstract	v
List of Figures	vi
List of Tables	viii

Chapter 1 Introduction	1
　1.1 Motivation	1
　1.2 Organization for the Thesis	2

Chapter 2 Intra Prediction and Inter Prediction in H.264	4
　2.1 Basic Concepts for Video CODEC of H.264	4
　2.2 Basic Concepts for Intra Prediction	6
　　2.2.1 Intra_4×4_Vertical Prediction Mode	9
　　2.2.2 Intra_4×4_Horizontal Prediction Mode	9
　　2.2.3 Intra_4×4_DC Prediction Mode	10
　　2.2.4 Intra_4×4_Diagonal_Down_Left Prediction Mode	11
　　2.2.5 Intra_4×4_Diagonal_Down_Right Prediction Mode	12
　　2.2.6 Intra_4×4_Vertical_Right Prediction Mode	13
　　2.2.7 Intra_4×4_Horizontal_Down Prediction Mode	14
　　2.2.8 Intra_4×4_Vertical_Left Prediction Mode	15
　　2.2.9 Intra_4×4_Horizontal_Up Prediction Mode	16
　2.3 Basic Concepts for Inter Prediction	17
　　2.3.1 Fractional Sample Interpolation Process	19

Chapter 3 Architecture of Intra 4×4 Prediction Sample Generator and Inter 4×4 Fractional Sample Interpolator	22
　3.1 Architecture of Intra 4×4 Prediction Sample Generator	22
　　3.1.1 Architecture of PE for Intra Prediction	23
　　3.1.2 Architecture of PE Array and Mask Generator	24
　　3.1.3 Architecture of PE for Intra DC Mode	27
　3.2 Software Process of Inter 4×4 Fractional Sample Interpolation	28
　3.3 Architecture of Inter 4×4 Fractional Sample Interpolator	30
　　3.3.1 Pipelined Architecture of Fractional Sample Interpolator	30
　　3.3.2 Architecture of Six-Tap Filter	31
　　3.3.3 Architecture of Two-Tap Filter	34
　　3.3.4 Architecture of PE Arrays	35
　　3.3.5 Multi-Cycle Architecture of Fractional Sample Interpolator	40
　　3.3.6 Controller Design of Multi-Cycle Architecture	41

Chgapter 4 Synthesis Result and Verification	46
　4.1 Synthesis Result of Intra 4×4 Prediction Sample Generator	46
　4.2 Synthesis Result of Inter 4×4 Fractional Sample Interpolator	47
　4.3 Verification	49
　　4.3.1 Verification Environment	49
　　4.3.2 RAM-base Interface Connection	50
　　4.3.3 Simulations	51
　4.4 Summary	55

Chapter 5 Conclusions and Future Work	56
　5.1 Conclusions	56
　5.2 Future Work	57

References	58
                                    

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校內：2006-08-24公開
校外：2006-08-24公開

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