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研究生： 陳柏穎
Chen, Po-Ying
論文名稱： 一個相容於標準CMOS製程並具有動態隨機存取記憶體核心的 嵌入式靜態隨機存取記憶體
An Embedded SRAM with DRAM Core in Standard CMOS Process
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 72
中文關鍵詞： 嵌入式 、記憶體
外文關鍵詞： embedded, memory
相關次數： 點閱：73  下載：6 
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    • 在本篇論文中，我們提出一個兼具動態隨機存取記憶體與靜態隨機存取記憶體優點並操作於200 MHz的嵌入式動態隨機存取記憶體。此設計除了可以減少面積成本外更可以降低製造成本。此外，將週期性更新操作隱藏執行，使其具有靜態隨機存取記憶體的介面，更提高了此記憶體在系統單晶片上的相容性。
    論文中描述使用中芯0.16微米標準製程所研製一個動態隨機存取記憶體中的記憶體區塊。由晶片量測結果顯示資料維持時間接近5.5毫秒，每一個記憶體區塊的消耗功率約為3毫瓦。而完整的嵌入式動態隨機存取記憶體使用台積0.16微米標準製程實現，新的記憶體單元及核心的面積分別為傳統6T-SRAM的百分之三十六以及百分之七十三。

    This thesis proposes a 200-MHz embedded dynamic random access memory (DRAM) that combines both the advantages of DRAM and static random access memory (SRAM). This design not only reduces the area cost but also saves the manufacturing cost. In additional, the design hides the periodically refresh operation in background and provides SRAM interface that make it easier to be embedded in a system-on-a-chip (SoC) design.
    A DRAM bank has been fabricated in SMIC standard 0.16-m 1P5M CMOS process. Measurement results show the retention time is nearly 5.5 ms and the power consumption is about 3 mW. The complete embedded DRAM has been fabricated in TSMC standard 0.16-m 1P5M CMOS process. The novel memory cell area and the whole core area are only 36 % and 73 % of a conventional 6T-SRAM, respectively.

    Abstract I Acknowledgement III List of Figures VI List of Tables IX Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Conventional Embedded Memory 2 1.2.1 Introduction to SRAM and DRAM 4 1.2.2 Blocks of Memory Architecture 7 1.3 Thesis Organization 12 Chapter 2 Embedded Memory Design with Differential Sensing Scheme 13 2.1 DRAM Core with SRAM Interface 13 2.2 Memory Bank Architecture 14 2.2.1 Differential Sensing Scheme 15 2.2.2 Cell with MOS Capacitor 16 2.2.3 Cell Characterization 17 2.2.4 Row Decoder with Predecoding Scheme 19 2.2.5 Sense Amplifier and Precharge Circuit 20 2.2.6 Control Circuit 25 2.2.7 Access Collision Policy 26 2.2.8 Other Circuits 27 2.3 Hiding Refresh Scheme 28 2.3.1 Refresh Timer 28 2.4 Simulation and Measurement Results 29 2.4.1 Simulation Results 30 2.4.2 Measurement Environment 32 2.4.3 Measurement Results 33 2.5 Summary 42 Chapter 3 Proposed Embedded Memory Design 43 3.1 Proposed Embedded Memory Architecture 43 3.2 Refresh Scheme 45 3.3 Memory Bank Architecture 47 3.3.1 Novel Memory Cell 48 3.3.2 Cell Characterization 51 3.3.3 Row Decoder with Predecoding Scheme 52 3.3.4 Sense Amplifier and Precharge Circuit 53 3.3.5 Control Circuit 56 3.3.6 Read/Write Buffers 57 3.3.7 Other Circuits 58 3.4 Peripheral Circuit 59 3.4.1 Bank Decoder 59 3.4.2 Refresh Timer 60 3.4.3 Refresh Address Counter 60 3.5 Simulation and Measurement Results 60 3.5.1 Simulation Results 62 3.5.2 Measurement Results 64 3.6 Summary 65 Chapter 4 Conclusion and Future Work 68 4.1 Conclusion 68 4.2 Future Work 69 Bibliography 70

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