在物聯網時代的來臨，隨著無線感測器網路需求量的增加。主要接收機持續性的醒著伴隨著功耗問題。因此，喚醒接收機的需求大幅提升。喚醒接收機是在接收到訊號後會再觸發主要接收機開始工作。這樣大部分時間主要接收機可以在睡眠狀態，從而降低功耗。因此，在喚醒接收機持續開著下，低功耗及高靈敏度則為設計上的挑戰。
本篇論文提出一個低功耗高靈敏度喚醒接收器。並且可以解調開關鍵控及頻率鍵移的調變訊號。在低功耗的設計下要提高靈敏度，第一級的低雜訊放大器的雜訊指數占很重要的角色。為了使功耗降低，使用次諧波降頻器，能夠有效降低本地振盪器的頻率及功耗。在第一次降頻後，透過帶有增益之多路徑混頻器可以同時達到降頻以及帶通濾波器的效果。在這多路徑混頻器中，同時包含著中心頻率的可調性，可以達到解調FSK訊號的需求。最後透過包絡檢測器及比較器解出喚醒訊號。在時脈產生器上，運用了四級環形振盪器來產生本地振盪頻率給次諧波混頻器。在除頻器中，運用了風車除頻器來同時除頻並改變占空比，可以大幅降低功耗。
本篇論文使用台積電90奈米互補式金屬氧化物半導體製程。工作於433百萬赫茲、資料傳輸率為每秒100千位元，達到-85 dBm的靈敏度，並且在電壓1伏特下功率消耗為184微瓦。

As the era of the Internet of Things (IoT) dawns, the demand for wireless sensor networks has significantly increased. The continuous operation of primary receivers is accompanied by power consumption issues. Therefore, the requirement for wake-up receivers (WuRxs) has risen substantially. WuRx trigger the primary receiver to start working upon receiving a signal. This allows the primary receiver to remain in a sleep mode most of the time, thereby reducing power consumption. Consequently, low power consumption and high sensitivity are design challenges for always-on WuRx.
This paper proposes a low-power high-sensitivity WuRx capable of demodulating on-off keying (OOK) and frequency-shift keying (FSK) modulation signals. To enhance sensitivity while maintaining low power consumption, the noise figure of the first stage low-noise amplifier (LNA) plays a crucial role. To reduce the power consumption, a sub-harmonic mixer is employed, effectively lowering the frequency and power consumption of the local oscillator (LO). After the downconversion, the gain enhanced N-path filter/mixer (NPFM) achieves both downconversion and band-pass filtering. This NPFM also includes frequency shift technique, meeting the requirements for demodulating FSK signals. Finally, an envelope detector and comparator decode the wake-up signal. For the clock generator, a four-stage ring oscillator generates the LO frequency to drive the sub-harmonic mixer. A windmill divider is used in the frequency dividers to simultaneously divide the frequency and change the duty cycle, significantly reducing power consumption.
This work is implemented using TSMC 90nm CMOS technology. Operating at 433 MHz with a data rate of 100 kbps, the receiver achieves a sensitivity of -85 dBm and a power consumption of 184 µW at a supply voltage of 1-V.

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