由於積體電路在設計的複雜度與產品上市時間的壓力上都快速地增加，使得用事先設計好的矽智產電路來設計系統單晶片成為縮短設計時程與降低開發成本的必要方法。然而，這些核心電路的供應者並不相同，並且各自擁有不一樣的設計方法與測試策略。矽智產電路除了在設計上要具有可重複使用的特性外，為了避免測試成為系統單晶片發展上的瓶頸，電路本身的測試技術同樣也要具備可重用性。因此，在這樣的需求下，發展一個可以解決系統單晶片測試整合問題的測試架構是必然的趨勢。
　　本論文提出一個同時支援掃描測試、記憶體內建式自我測試與類比數位轉換器內建式自我測試電路的單晶片系統測試平臺用以解決測試整合上的問題。其主要概念是利用在單晶片系統中原本就存在的嵌入式處理器來執行一個測試程式以控制整個測試流程。同時藉由一些輔助電路的幫助，對晶片中的核心電路進行結構性測試(structural testing)與類比數位轉換器的測試。此外，有一些複雜的核心電路是以階層式的概念來構築電路的結構。因此，在本論文中也同時提出一個測試架構來解決階層式測試控制的問題。另外，我們也提供測試整合軟體來降低整合流程的複雜度。

　　The rapid increase in IC design complexity and time-to-market pressure leads to the necessity of reusing pre-defined cores to develop new SOC design. In general, many of these cores come from the third party vendors which may have different design and test strategies. To prevent the testing from becoming the bottleneck of SOC manufacturing process, not only the core design but also the core test should be reusable. For these reasons, developing a test architecture to deal with the test integration problem for SOC is a natural trend.
　　In this thesis, we present a SOC test platform that can support the various types of test methodologies including scan-based testing, memory BIST and ADC BIST. An embedded processor is employed as a control kernel to execute a test program in this platform. The program handles the structural testing of the digital cores and the testing of ADC cores with the assistance of some extra circuitry. Besides, some cores may have hierarchical structure, which means one complex core may in turn be composed of multiple cores. Therefore, we also develop a new hierarchical test control architecture, called the Hierarchical Test Control System (HTCS), to solve the hierarchical test problem. In order to ease the complex integration flow, we have also developed a set of test integration tools to automate the test platform development.

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