電腦視覺領域的進步使得各種智慧應用成為可能。對於有些產品，需要使用低 複雜度的物件偵測器，例如無線傳感器網絡或智能玩具，這為硬體設計工程師帶來 了挑戰。這篇論文中，我們提出一個基於 Viola-Jones 演算法的基礎設計。為了在保 持足夠計算吞吐量的同時減小面積，晶片片上記憶體(例如 SRAM)被劃分為多個 區塊。但是由於記憶體往往只有寥寥幾個存取埠，對同一區塊的存取可能會發生衝 突。由於物件偵測演算法在機器學習上的不確定性，導致的記憶體存取是不規律的， 因而我們無法以傳統方式將記憶體劃分為多個區塊。因此，我們提出了一種方法， 能夠對機器學習後產生的記憶體存取序列做排程，進而避免記憶體存取衝突。我們 用一個 FPGA 實現驗證該作法，結果表明，通過使用所提出的方法，可以大大減少 正反器的使用率。此外，整體面積效率也得到改善。

Advances in the computer vision have enabled various smart applications in the con- sumer market. Some products, such as wireless sensor networks or smart toys, may require a low-complexity visual object detection unit, in which area and energy efficiency are of con- cerned. This poses a challenge to the designers. In this work, a flexible yet area-efficient object detector based on Viola-Jones algorithm is presented as a base design. To reduce the area while maintaining sufficient throughput, on-chip memories (such as SRAM) are par- titioned into several banks. However, accesses to the same bank may conflict, since the accessing port of each banks are limited. Resolving conflicts is non-trivial due to the fact that the memory access pattern of the detection task depends on the result of machine learn- ing, which is often unpredictable before training. Therefore, we propose an approach which explicitly schedules the access sequence as a post-processing performed after training the object model. As a consequence, memory access conflicts can be avoided. An FPGA imple- mentation is used to verify the idea, and is given at the end of this study. The result shows that by using the proposed methodology, the flip-flop utilization can be drastically reduced. Moreover, the overall area-efficiency is also improved.

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