隨著低功率微處理器系統的發展，衍生出無線人體區域網路與物聯網等新興的應用型態，而在這類低工作週期型應用中，系統的處於閒置時的待機功率往往佔據系統總能量消耗的一大部分，而近年來出現非揮發性微處理器利用非揮發性記憶體斷電後仍能維持儲存資料的特色，可降低以電源切斷做為低功率模式的額外代價，使系統可透過電源切斷降低待機功率造成的影響。然而在近幾年與非揮發性微處理器相關的研究，大部分只考量到微處理器系統中硬體的部分，而造成較大的功率消耗與面積額外代價以及通訊界面不同步與時間認知差異等潛在的例外狀況。本論文以系統運行的角度觀察並提出考量軟硬體交互作的非揮發性微處理器實現方法，透過可編程的例外處理程序、系統狀態分類及選擇性儲存操作等機制，解決系統例外狀況產生並與最近研究文獻中性能指標最好的實現方式相比，可降低32%使用的非揮發性正反器數量，21~53%的系統儲存能量消耗，35%的系統恢復能量消耗，並降低42%額外面積代價。

Applications of ultralow-power microprocessors such as internet of things and wireless body area network are rapidly developing. In these applications, systems operating most of its time in standby mode, so it is more critical to reduce the energy consumption during standby mode. Nonvolatile microprocessors (NVPs) are one of promising candidates for such kinds of circumstances because NVPs have characteristics like instant on/off, zero standby power and resilient to power failures. However, recent studies only consider the hardware part on NVPs without considering the impacts on system operation. The lack of software consideration may result in not only system instability, but also energy consumption and area overhead. The thesis proposes an effective method that considers the interaction of software and hardware simultaneously for NVPs. Specifically, three techniques are developed and evaluated. One is to handle the process of programmable states recovery exception. Another one is to reduce NV storage by intelligently partitioning system states. The other is to eliminate redundancy store operations. State-of-the-art approaches for NVPs and the proposed one are realized on the same baseline architecture that is consisting of a MSP430 microprocessor and the same nonvolatile memory cells. We evaluate these approaches with a figure-of-merit (FOM) consisted of energy, delay and area. The proposed method not only outperforms others in the FOM, but also decreases system store energy by 21~53%, system restore energy by 35% and achieves 42% area overhead reduction when compared to the design of the second place.

[1] C.-J. Deepu, X.-Y. Xu, X.-D. Zou, L.-B. Yao, and Y. Lian. “An ECG-on-Chip for Wearable Cardiac Monitoring Devices,” in Proc. IEEE International Symposium on Electronic Design, Test and Application, pp. 225–28, 2010.
[2] R. Erich. “Trends in Microelectronic Assembly for Implantable Medical Devices,” in Proc. Electronic Manufacturing Technology Symposium, pp.103–7, 2007.
[3] A. Maciuca, G. Stamatescu, D. Popescu, and M. Strutu. “Integrating Wireless Body and Ambient Sensors into a Hybrid Femtocell Network for Home Monitoring,” in Proc. International Conference on Systems and Computer Science (ICSCS), pp. 32–37, 2013.
[4] K. Gill, S.-H. Yang, F. Yao, and X. Lu. “A Zigbee-Based Home Automation System,” in IEEE Transactions on Consumer Electronics, vol. 55, pp. 422–30, 2009.
[5] F. Casamassima, E. Farella and L. Benini. “Power Saving Policies for Multipurpose WBAN,” in Proc. International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), pp.83–90, 2013.
[6] C. C. Y. Poon, Y.-T. Zhang, and S.-D. Bao. “A Novel Biometrics Method to Secure Wireless Body Area Sensor Networks for Telemedicine and M-Health,” in IEEE Trans. on Communications Magazine, vol.22, pp.73–81, 2006.
[7] G.-l. Sun, J.-l. Yu, Z. Ying, and W.-X. Li. “Design and Implementation of Sensor Nodes for a Wireless Body Area Network,” in Proc. International Conference on Biomedical Engineering and Informatics (BMEI), pp.1403–1406, 2011.
[8] N. Bari, G. Mani, and S. Berkovich. “Internet of Things as a Methodological Concept,” in Proc. International Conference on Computing for Geospatial Research and Application, pp. 48–55, 2013.
[9] M. Jiménez et al., ”Fundamentals of Interfacing,” in Introduction to Embedded Systems, pp.249-295, 2013.
[10] W.-K. Yu, S. Rajwade, S.-E. Wang, B. Lian, G.E. Suh, E. Kan. A Non-Volatile Microcontroller with Integrated Floating-Gate Transistors [Online]. Available: http://webhost.laas.fr/TSF/WDSN11/WDSN11_files/Slides/WDSN11_33-Yu.pdf.
[11] Y. Wang, Y. Liu, S. Li, X. Sheng, D. Zhang, M.-F. Chiang, B. Sai, X.-S. Hu, and H. Yang. “PaCC: A Parallel Compare and Compress Codec for Area Reduction in Nonvolatile Processors,” in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol.22, pp.1491-1505, 2014.
[12] W. Yu, S. Rajwade, S.-E. Wang, B. Lian, G.-E. Suh, and E. Kan, “A non-volatile microcontroller with integrated floating-gate transistors,” in Proc. International Conference on Dependable Systems and Networks Workshops (DSN-W),pp.75-80, 2011.
[13] M. Zwerg, A. Baumann, R. Kuhn, M. Arnold, R. Nerlich, M. Herzog, R. Ledwa, et al. “An 82 uA/MHz Microcontroller with Embedded FeRAM for Energy-Harvesting Applications,” in Proc. IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.334–36, 2011.
[14] M. Qazi, A. Amerasekera, and A.P. Chandrakasan. “A 3.4pJ FeRAM-Enabled D Flip-Flop in 0.13um CMOS for Nonvolatile Processing in Digital Systems,” in Proc. IEEE International Solid-State Circuits Conference (ISSCC), pp.192–193, 2013.
[15] N. Sakimura, T. Sugibayashi, R. Nebashi, and N. Kasai. “Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs,” in Proc. IEEE Custom Integrated Circuits Conference (CICC), pp.355–358, 2008.
[16] I. Kazi, P. Meinerzhagen, P.-E. Gaillardon, D. Sacchetto, A. Burg, and G. De Micheli. “A ReRAM-Based Non-Volatile Flip-Flop with Sub-VT Read and CMOS Voltage-Compatible Write,” in Proc. New Circuits and Systems Conference (NEWCAS), pp. 1–4, 2013.
[17] Y. Wang, Y. Liu, S. Li, D. Zhang, B. Zhao, M.-F. Chiang, Y. Yan, B. Sai, and H. Yang. “A 3us Wake-up Time Nonvolatile Processor Based on Ferroelectric Flip-flops,” in Proc. European Solid-State Circuits Conference (ESSCIRC), pp.149–152, 2012.
[18] N. Sakimura1, Y. Tsuji1, R. Nebashi1, J. A. Rodriguez, and H. P. McAdams, “A 90nm 20MHz Fully Nonvolatile Microcontroller for Standby-Power-Critical Applications,” in Proc. International Solid-State Circuits Conference (ISSCC), pp. 250–252, 2014.
[19] Y. Wang, Y. Liu, Y. Liu, D. Zhang, S. Li, B. Sai, M.-F. Chiang, and H. Yang. “A Compression-based Area-efficient Recovery Architecture for Nonvolatile Processors,” in Proc. Design, Automation Test in Europe Conference Exhibition (DATE), pp.1519–1524, 2012.
[20] S.C. Bartling, S. Khanna, M.P. Clinton, S.R. Summerfelt, J.A. Rodriguez, and H.P. McAdams. “An 8MHz 75 uA/MHz Zero-leakage Non-volatile Logic-based Cortex-M0 MCU SoC Exhibiting 100% Digital State Retention at VDD=0V with <400ns Wakeup and Sleep Transitions,” in Proc. International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), pp.432–433, 2013.
[21] S. Khanna, S.C. Bartling, M. Clinton, S. Summerfelt, J.A. Rodriguez, and H.P. McAdams. “An FRAM-Based Nonvolatile Logic MCU SoC Exhibiting 100% Digital State Retention at 0 V Achieving Zero Leakage With 400-Ns Wakeup Time for ULP Applications,” in IEEE J. Solid-State Circuits, vol. 49, pp. 95-106, 2014.
[22] Warren A. Hunt, Jr. “Microprocessor Design Verification,” in J. Automated Reason, vol. 5, pp.429-460, 1989.