隨著人工智能模型和算法變得越來越複雜，運算硬體設計也在不斷更新和改進。除了通過工藝技術進步提高AI運算晶片的運行速度外，整體架構設計也是提升性能的關鍵。本論文基於一個假設，即未來有可能開發出3D堆疊晶圓級高性能計算系統，該系統通過堆疊多個晶圓級晶片而形成一個極其強大的AI計算系統。這樣的系統很可能在不久的將來被引入到百億級超級計算設施中。當然，要讓如此復雜的系統在實踐中變得可行，我們需要解決一個關鍵的良率問題，即由於嵌入式存儲器而產生的特定問題。在本論文中，我們強調了此類系統之品質和可靠性，並在系統級提出了一種新穎的3D內建自行修復(3D-BISR)架構，該架構是在我們現有的2D BISR方案之上提出。我們的3D-BISR的關鍵特性是3D相互修復功能。從我們的模擬結果來看，通過在3D相鄰的內建記憶體之間共享備用資源，我們可以提高修復率，也提高內建記憶體在這種3D堆疊晶圓級高性能計算系統中的良率和壽命。我們還提出了總共 6 種 3D 備用資源分配（3D-RA）方案，用於有效分配備用資源，同時平衡系統可靠性和內建記憶體修復成本。我們的實驗結果顯示，使用我們提出的3D-BISR (六個共享模式)可以實現比傳統BISR高30%的修復率。如果我們將其與3D-BISR（單一共享模式）情況進行比較，它可以實現高達5%的提升。至於與最佳解的比較，我們的結果只比它少0.2%。對於壽命的實驗，使用我們提出的3D-BISR (六個共享模式)可以實現比傳統BISR多30%的壽命。如果我們將其與3D-BISR（單一共享模式）情況進行比較，它可以實現高達5%的提升。至於與最佳解的比較，我們的結果只少了0.3%。

As AI models and algorithms are becoming more and more complex, computing hardware designs are constantly being updated and improved. In addition to improving the operation speed of AI computing chips through process technology advancement, the overall architecture design is also a key to improving performance. This thesis is based on an assumption that a 3D stacked wafer-scale high performance computing system is likely to be developed in the future, which is created by stacking multiple wafer-scale chips to form an extremely powerful AI computing system. Such a system is likely to be introduced to exa-scale super-computing facilities in the near future. Of course, for such a complicated system to become feasible in practice, we need to solve one of the critical yield problems, i.e., the specific one that is due to the embedded memories. In this thesis, we stress the memory quality and reliability of such systems, and propose a novel 3D built-in self-repair (3D-BISR) architecture at the system level, which is proposed on top of existing 2D BISR scheme. The key feature of our 3D-BISR is the 3D peer-repair capability. From our simulation results, we show that, by sharing spare resources among the embedded memories in the 3D neighborhood, we can improve the repair rate, and thus the yield and lifetime, of the embedded memories in such 3D stacked wafer-scale high performance computing systems. We also propose a total of six schemes for 3D redundancy allocation (3D-RA), which are for effective allocation of spare memory resources that also balance between system reliability and memory repair costs. Our experimental results show that the proposed 3D-BISR with all six schemes can achieve a memory repair rate that is 30% higher than the conventional BISR. If we compare it with the 3D-BISR of a single scheme, the repair rate increase is up to 5%. Our result is only 0.2% lower than the optimal solution. From the experimental result for lifetime, the 3D-BISR with all six schemes can achieve a lifetime that is 30% longer than the conventional BISR. If we compare it with the 3D-BISR of a single scheme, the lifetime increase is up to 5%. The result is only 0.3% lower than the optimal solution.

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