本論文設計研製60 GHz CMOS寬頻低雜訊放大器與24 GHz CMOS低雜訊放大器使用具抑制電磁干擾之蜂巢型電感。論文主要分為兩部份:第一部份包含低雜訊放大器的簡介與重要參數介紹，接著為60 GHz CMOS寬頻低雜訊放大器的設計流程與實際量測結果；第二部份為具抑制電磁干擾之蜂巢型電感簡介與將此電感使用於24 GHz CMOS低雜訊放大器設計與實際量測結果。
60 GHz CMOS寬頻低雜訊放大器主要電路架構為串接四級疊接組態放大器，而匹配網路使用薄膜微帶線來取代電感與部份電容，可降低整體面積，同時提升整體設計之精準度。在輸入與輸出匹配網路採用型網路，達成寬頻特性，並在疊接放大器中的共閘極放大器的閘極端，加上一段等效為電感特性的微帶線，提升整體增益。此60 GHz CMOS寬頻低雜訊放大器採用標準TSMC 90 nm CMOS製程製作。量測結果顯示，最高增益為23 dB，頻寬達12 GHz (55-67 GHz)，而最低之雜訊指數為6.4 dB，輸入1-dB壓縮功率IP1dB為-26 dBm，IIP3為-15.7 dBm，整體晶片面積為0.6 mm2，電源電壓採用1.8 V，整體功率消耗為20.1 mW。
24 GHz CMOS低雜訊放大器特點在於使用具抑制電磁干擾能力之蜂巢型電感，蜂巢型電感因特殊的結構設計，擁有磁場感應相互抵銷的能力，不僅能降低電感對外界的干擾，也能抑制外來磁場的干擾。電路主要架構為疊接式源極電感退化架構，其中源極電感使用蜂巢型電感，此低雜訊放大器電路符合24 GHz ISM頻帶的應用需求。晶片採用標準TSMC 0.18 um CMOS製程製作，量測結果顯示最高增益為8.55 dB，雜訊指數約為4 dB，IP1dB與IIP3分別為-11 dBm與-3 dBm。單一24 GHz CMOS低雜訊放大器所佔面積為0.59 mm2，電源電壓採用1.8 V，功率消耗為5.72 mW。與使用傳統型電感的放大器比較，本論文所設計之24 GHz低雜訊放大器使用蜂巢型電感，有優於10-15 dB的抑制電磁干擾效果。

The designs of 60 GHz CMOS wideband low noise amplifier (LNA) and 24 GHz CMOS LNA with an EMI suppression honeycomb-shaped inductor are presented in this thesis. The thesis mainly contains two parts. The first part of the thesis is about the introduction to an LNA and the related key parameters. The followed is the design flow and the experimental results of a 60 GHz CMOS wideband LNA. The second part is to introduce the electromagnetic interference suppression (EMI) honeycomb-shaped inductor and to discuss the design of 24 GHz CMOS LNA integrated with the honeycomb-shaped inductor and the experimental results.
The structure of the 60 GHz CMOS wideband LNA is composed of 4 stages of cascode amplifiers. For the purpose of reducing the occupied area and increasing the success of circuit function, the matching networks are implemented with the thin-film microstrip (TFMS) lines instead of the lumped inductors and capacitors. The π type topology is adopted in the input and output matching networks to realize the wideband operation. In addition, a section of microstrip line as an inductor is placed at the gate terminal of the common gate stage in each cascode amplifier to improve the circuit performance. The 60 GHz CMOS wideband LNA has been fabricated in TSMC 90 nm standard process. The measured maximum gain is 23 dB with the available bandwidth of 12 GHz (55-67 GHz). The measured minimum noise figure (NF) is 6.4 dB and the IP1dB is -26 dBm, respectively. The chip size is 0.6 mm2. With supply voltage of 1.8 V and the overall dc power consumption is 20.1 mW.
The 24 GHz LNA features an integration with an EMI suppression honeycomb-shaped inductor. With the unique layout, the induced voltages of the sub-coils due to the magnetic flux linked through the honeycomb-shaped inductor from the adjacent inductors will be cancelled, therefore the honeycomb-shaped inductor is able to provide magnetic field induction cancellation. On the other hand the inductor has an even number of anti-direction magnetic dipole moments to reduce the magnetic flux linked to the adjacent device. The honeycomb-shaped inductor also can prevent from the expansion of inner magnetic flux and thus can suppress the influence to the adjacent devices at the same time. Cascode topology with source inductive degeneration is adopted in the 24 GHz LNA design, wherein the honeycomb-shaped inductor is used as the source inductor.
The 24 GHz LNA has been fabricated in TSMC 0.18 um CMOS process. The measured maximum gain and minmum NF are 8.55 dB and 4 dB, respectively. The measured IP1dB is -11 dBm and IIP3 is -3 dBm. The chip size is 0.59 mm2. With a supply voltage of 1.8 V, the dc power consumption is 5.72 mW. The 24 GHz LNA with a honeycomb-shaped inductor is proved to exhibit a better EMI suppression than the LNA with a conventional inductor over 10-15 dB.

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