本論文以硬體電路實現具模糊推論與自我學習能力之適應性類神經模糊網路運算架構，並發展出可於晶片上即時學習之電路，以提供實際應用之有效解決方案。為實現高效能電路，此硬體模組架構設計方式，採用系統化高階合成設計概念。首先，深入分析具平行運算之資料流結構及同時處理之控制機制，再利用整數線性規劃演算法求得最佳化排程與配置，最後，將資料流設計成細密管線式(fine grain pipeline)架構，並採用全域性非同步與區域性同步(globally-asynchronous locally-synchronous)之控制方法，藉以改善電路執行速度、資料溝通的強健性及提升控制器運算處理能力。演算法化簡和資料流計算結果共用，皆有利於節省硬體資源並達到高運算效能。此電路運用在倒傳遞電路設計上，更能大幅增強此複雜架構之執行能力。此外，遵循矽智財(IP)設計的共同規範和原則，將此適應性類神經模糊網路電路發展成高彈性、可配置且可重複使用的硬體資源，建立完整之設計文件，使其具有易於系統整合之優越性。最後，實現成FPGA原型電路，利用軟硬體共模擬平台，將此電路實際測試於智慧型駕車系統之控制，以驗證其效能。

This thesis focuses on a digital hardware implementation of an adaptive neuro-fuzzy network with on-chip learning capability. We adopt a backpropagation learning algorithm to optimize the network parameters. To minimize the computational time and resources, we proposed to share the computational results in both feedforward and backpropagation paths. That is, the results of data computation required in the feedforward path are stored in buffers to establish a database that enables the backpropagation circuit to retrieve the necessary data when calculating the error gradients. This improvement leads to a simpler data flow and the reduction of resource consumption. Then we adopt an integer linear programming to obtain an optimal schedule. After the data path analysis, we divide feedforward path into three asynchronous parts to reduce power consumption and prevent the problem of clock skew. Each part is realized by a synchronous fine-grain pipeline architecture to get high computational speed. The backpropagation learning path, however, is simply a synchronous pipeline architecture because of the continuous update process and resource limitation. In addition, we follow the guidelines of silicon intellectual property so that our circuit can become a reusable, flexible, and configurable module for system integration. To verify the circuit, we implement the circuit in a FPGA develop board and validate the effectiveness in an intelligent car-driving system. The simulation results have shown that our circuit performs well in speed, accuracy, and resource sharing.

[1]J. S. Wang and C. S. George Lee, “Self-adaptive neuro-fuzzy inference systems for classification applications,” IEEE Trans. on Fuzzy Systems, vol. 10, no. 6, pp. 790-802, Dec. 2002.
[2]J. S. Wang and C. S. George Lee, “Self-adaptive recurrent neuro-fuzzy control of an autonomous underwater vehicle,” IEEE Trans. on Robotics and Automation, vol. 19, no. 2, pp. 283-295, Apr. 2003.
[3]A. Rubaai, R. Kotaru, and M. D. Kankam, “A continually online-trained neural network controller for brushless dc motor drives,” IEEE Trans. on Industry Applicatations, vol. 36, pp. 475-483, Mar.-Apr. 2000.
[4]J. S. Wang and C. S. George Lee, “Efficient neuro-fuzzy control systems for autonomous underwater vehicle control,” Proc. of the 2001 IEEE Int. Conf. on Robotics & Automation Seoul, vol. 3, pp. 2986-2991, May 2001.
[5]M. Y. Chen and D. A. Linkens, “A systematic neuro-fuzzy modeling framework with application to material property prediction,” IEEE Trans. on System, vol. 31, no.5, pp. 781-790, Oct. 2001.
[6]S. Zahan and C. Michael, “A fuzzy hierarchical approach to medical diagnosis,” Proc. of the 6th IEEE Int. Conf. on Fuzzy Systems, vol. 1, pp. 319-324, July 1997.
[7]Z. Ali and C. S. Lee, “Design of multimedia web server using a neuro-fuzzy framework,” Proc. of the 9th IEEE Int. Conf. on Fuzzy Systems, vol. 1, pp. 510-515, May 2000.
[8]H. Ghezzelayagh and K. Y. Lee, “Intelligent predictive control of a power plant with evolutionary programming optimizer and neuro-fuzzy identifier,” Proc. of the 2002 Congress on Evolutionary Computation, vol. 2, pp. 1308-1313, May 2002.
[9]S. K. Sinha and F. Karray, “Classification of underground pipe scanned images using feature extraction and neuro-fuzzy algorithm,” IEEE Trans. on Neural Networks, vol. 13, no. 2, pp. 393-401, Mar. 2002.
[10]A. Joshi and E. N. Houstis, “On neurobiological, neuro-fuzzy, machine learning, and statistical pattern recognition techniques,” IEEE Trans. on Neural Networks, vol. 8, no. 1, pp. 18-31, Jan. 1887.
[11]A. Costa, A. D. Gloria, and M. Olivieri, “Hardware design of asynchronous fuzzy controllers,” IEEE Trans. on Fuzzy Systems, vol. 4, no. 3, Aug. 1996.
[12]R. P. Palmer and P. A. Rounce, “An architecture for application specific neural network processors,” Computing & Control Engineering Journal, vol. 5, no. 6, pp. 260-264, Dec. 1994.
[13]Q. Wang, B. Yi, Y. Xie, and B. Liu, “The hardware structure design of perceptron with FPGA implementation,” Proc. of the IEEE Int. Conf. on Systems, Man and Cybernetics, vol. 1, pp. 762-767, Oct. 2003.
[14]M. Porrmann, U. Witkowski, H. Kalte, and U. Ruckert, “Implementation of artificial neural networks on a reconfigurable hardware accelerator,” Proc. 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing, pp. 243-250, Jan. 2002.
[15]K. Uchimura, O. Saito, and Y. Amemiya, “A high-speed digital neural network chip with low-power chain-reaction architecture,” IEEE Journal of Solid-State Circuit, vol. 27, no. 12, pp. 1862-1867, Dec. 1992.
[16]C. H. Kung, M. J. Devaney, C. M. kung, C. M. Huang, Y. J. Wang, and C. T. Kuo, “The VLSI implementation of an artificial neural network scheme embedded in an automated inspection quality management system,” Proc. of the 19th IEEE Instrumentation and Measurement Technology Conf., vol. 1, pp. 239-244, May 2002.
[17]A. Bermak and A. Bouzerdoum, “VLSI implementation of a neural network classifier based on the saturating linear activation function,” Proc. of the 9th IEEE Int. Conf. on Neural Information Processing, vol. 2, pp. 981-985, Nov. 2002.
[18]S. Vitabile, V. Conti, F. Gennaro, and F. Sorbello, “Efficient MLP digital implementation on FPGA,” Proc. of 8th Euromicro Conf. on Digital System Design, pp. 218-222, Aug. 2005.
[19]J. Weiwei, J. Dongming, and Z. Xun, “VLSI design and implementation of a fuzzy logic controller for engine idle speed,” Proc. of 7th IEEE Int. Conf. on Solid-State and Integrated Circuits Technology, vol. 3, pp. 2067-2070, Oct. 2004.
[20]M. Marchesi, G. Orlandi, F. Piazza, L. Pollonara, and A. Uncini, “Multi-layer perceptrons with discrete weights,” Int. Joint Conf. on Neural Networks, vol. 2, pp. 623-630, June 1990.
[21]S. Himavathi and B. Umamaheswari, “New membership functions for effective design and implementation of fuzzy systems,” IEEE Trans. on Systems, Man, and Cybernetics, part A, vol. 31, no. 6, Nov. 2001.
[22]L. M. Reyneri, “Implementation issues of neuro-fuzzy hardware: going toward HW/SW codesign,” IEEE Trans. on Neural Networks, vol. 14, no. 1, pp. 176-179, Jan. 2003.
[23]S. McLoone and G. W. Irwin, “Fast parallel off-line training of multilayer perceptrons,” IEEE Trans. on Neural Networks, vol. 8, pp. 647-653, May 1997.
[24]T. Szabo, L. Antoni, G. Horvath, and B. Feher, “A full-parallel digital implementation for pre-trained NNs,” Proc. of the IEEE-INNS-ENNS Int. Joint Conf. on Neural Networks, vol. 2, pp. 49-54, July 2000.
[25]H. Faiedh, Z. Gafsi, K. Torki, and K. Besbes, “Digital hardware implementation of a neural network used for classification,” Proc. of the 16th IEEE Int. Conf. on Microelectronics, pp. 551-554, Dec. 2004.
[26]T. Lehmann, R. Woodburn, and A. F. Murray, “On-chip learning in pulsed silicon neural networks,” Proc. of IEEE Int. Symposium on Circuits and Systems, vol. 1, pp. 693-696, June 1997.
[27]T. Morie and Y. Amemiya, “An all-analog expandable neural network LSI with on-chip backpropagation learning,” IEEE Journal of Solid-State Circuits, vol. 29, no. 9, pp. 1086-1093, Sept. 1994.
[28]A. J. Montalvo, R. S. Gyurcsil, and J. J. Paulos, “An analog VLSI neural network with on-chip perturbation learning,” IEEE Journal of Solid-State Circuits, vol. 32, no. 4, pp. 535-543, Apr. 1994.
[29]T. Kamio, S. Tanaka, and M. Morisue, “Backpropagation algorithm for logic oriented neural networks,” Proc. of the IEEE-INNS-ENNS In. Joint Conf. on Neural Networks, vol. 2, pp. 123-128, July 2000.
[30]T. Schoenauer, S. Atasoy, N. Mehrtash, and H. Klar, “NeuroPipe-Chip: A digital neuro-processor for spiking neural networks,” IEEE Trans. on Neural Networks, vol. 13, no. 1, pp. 205-213, Jan. 2002.
[31]Y. Yi, D. M. Vilathgamuwa, and M. A. Rahman, “Implementation of an artificial-neural-network-based real-time adaptive controller for an interior permanent-magnet motor drive,” IEEE Trans. on Industry Applications, vol. 39, no. 1, pp. 96-104, Jan.-Feb. 2003.
[32]R. G. Girones and A. M. Salcedo, “Systolic implementation of a pipelined on-line backpropagation,” Proc. of the 7th Int. Conf. on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems, pp. 387-394, Apr. 1999.
[33]C. Z. Tang and H. K. Kwan, “Multilayer feedforward neural networks with single powers-of-two weights,” IEEE Trans. on Signal Processing, vol. 41, no. 8, pp. 2724-2727, Aug. 1993.
[34]A. Bermak and D. Martinez, “Digital VLSI implementation of a multi-precision neural network classifier,” Proc. of 6th IEEE Int. Conf. on Neural Information Processing, vol. 2, pp. 560-565, Nov. 1999.
[35]H. F. Restrepo, R. Hoffmann, A. Perez-Uribe, C. Teuscher, and E. Sanchez, “A networked FPGA-based hardware implementation of a neural network application,” IEEE Symposium on Field-Programmable Custom Computing Machines, pp. 337-338, Apr. 2000.
[36]S. Bitabile, A. Gentile, G. Dammone, and F. Sorbello., “MLP neural network implementation on a SIMD architecture,” Lecture Notes in Computer Science, vol. 2486, pp. 99-108, 2002.
[37]S. Bitabile, A. Gentile, and F. Sorbello., “Real-time road signs recognition on a SIMD architecture,” WSEAS Trans. on Circuits and Systems, vol. 3, no. 3, pp. 664-669, May 2004.
[38]C. T. Lin and C. S. G. Lee, Neural Fuzzy Systems: A Neuro-Fuzzy Synergism to Intelligent Systems, Prentice Hall PTR, 1996.
[39]K. S. Narendra and K. Parthasarathy, “Identification and control of dynamical systems using neural networks,” IEEE Trans. on Neural Networks, vol. 1, no. 1, pp. 4-47, Mar. 1990.
[40]P. G. Paulin and J. P. Knight, “Algorithms for high-level synthesis,” IEEE Trans. on Design & Test of Computers, vol. 6, no. 6, pp. 18-31, Dec. 1989.
[41]D. D. Gajski, N. D. Dutt, and B. M. Pangrle, “Silicon compilation,” Proc. Custom Integrated Circuits Conf., pp. 102-110, May 1986.
[42]G. D. Micheli, Synthesis and Optimization of Digital Circuits, McGRAW-HILL, 1994.
[43]C. T. Hwang, J. H. Lee, and Y. C. Hsu, “A formal approach to the scheduling problem in high level synthesis,” IEEE Trans. on Computer-Aided Design, vol. 10, no. 4, Apr. 1991.
[44]S. Bakshi and D. D. Gajski, “Partitioning and pipelining for performance-constrained hardware/software systems,” IEEE Trans. on Very Large Scale Integration System, vol. 7, no. 4, Dec. 1999.
[45]R. Manohar, T. K. Lee, and A. J. Martin, “ Projection: a synthesis technique for concurrent systems,” Proc. of 5th Int. Symposium on Advanced Research in Asynchronous Circuits and System, pp. 125-134, Apr. 1999.
[46]M. D. Ciletti, Advanced Digital Design with The Verilog HDL, Prentice-Hall, 2003.
[47]J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Digital Integrated Circuits: A Design Perspective, 2nd ed., Upper Saddle River, Prentice-Hall, 2003.
[48]M. Keating and P. Bricaud, Reuse Methodology Manual, Kluwer Academic Publishers, 2002.
[49]R. Manohar and C. Kelly IV, “Network on a chip: modeling wireless networks with asynchronous VLSI,” IEEE Communications Magazine, vol. 39, no. 11, pp. 149-155, Nov. 2001.
[50]J. Teifel and R. Manohar, “An asynchronous dataflow FPGA architecture,” IEEE Trans. on Computers, vol. 53, no. 11, Nov. 2004.
[51]H. Qi, Z. Jiang, and J. Wei, “IP reusable design methodology,” Proc. of 4th IEEE Int. Conf. on ASIC, pp. 756-759, Oct. 2001.
[52]M. Martina, A. Molino, and F. Vacca, “FPGA system-on-chip soft IP design: a reconfigurable DSP,” Proc. of 45th Midwest Symposium on Circuits and Systems, vol. 3, pp. 4-7, Aug. 2002.
[53]S. Pillement, D. Chillet, and O. Sentieys, “Behavioral IP specification and integration framework for high-level design reuse,” Proc. of Int. Symposium on Quality Electronic Design, pp. 388-393, Mar. 2002.
[54]A. Hekmatpour, K. Goodnow, and S. Hemen, “Standards-compliant IP-based ASIC and SoC design,” Proc. of IEEE Int. Conf. on SOC, pp. 322-323, Sept. 2005.
[55]J. H. Lin, A Neuro-Fuzzy Network with Online Learning Capability: Asynchronous Pipeline Hardware Design, M.S. Thesis, Department of Electrical Engineering, National Cheng Kung Univ., Tainan, Taiwan, 2005.
[56]L. Y. Chiou, S. Bhunia, and K. Roy, “Synthesis of application-specific highly efficient multi-mode systems for low-power applications,” Design, Automation and Test in Europe Conf. and Exhibition, pp. 96-101, 2003.
[57]G. D. Micheli, Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994.
[58]A. Davis and Nowick SM, “An introduction to asynchronous circuit design,” Technical Report UUCS97-013, University of Utah, pp. 1-58, Sept. 1997.
[59]Y. Ying, Z. Lei, and M. Hao, “Design and VLSI implementation of an asynchronous low power microcontroller,” Proc. of the 4th IEEE Int. Conf. on ASIC, pp. 797-799, 23-25 Oct. 2001.
[60]S. Hauck, “Asynchronous design methodologies: an overview,” Proc. of the IEEE, vol. 83, no. 1, pp. 69-93, Jan. 1995.