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研究生： 黃冠穎
Huang, Guan-Ying
論文名稱： 應用於二位元低密度同位元解碼器之洗牌隨機運算變數節點設計
Shuffle-based Stochastic Variable Node Design for Binary LDPC
指導教授： 謝明得
Shieh, Ming-Der
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2018
畢業學年度： 106
語文別： 英文
論文頁數： 60
中文關鍵詞： 二位元低密度同為檢查碼 、隨機運算 、邊緣記憶體 、洗牌機制之邊緣記憶體
外文關鍵詞： Low-density check parity code, stochastic computing, edge memory, shuffle-based edge memory
相關次數： 點閱：56  下載：3 
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    • 隨機計算應用於二位元低密度同位元檢查碼(Binary Low-Density Parity-Check, LDPC)的實現上以利於降低硬體實現的複雜度。

    對比傳統二位元低密度同位元檢查碼解碼器計算單元的複雜電路，在隨機變數域當中皆可利用簡易邏輯匣電路實現。但是隨機變數計算中所需符合的資料間彼此獨立的特性，會因為同位元檢查矩陣的設計和遞迴疊代計算而被破壞。本論文提出的洗牌機制(Shuffle mechanism)，是針對隨機變數域(Stochastic computing domain)二位元低密度同位元檢查碼當中的變數點運算單元做設計，此方法是將最早提出的邊緣記憶體(Early edge memory)作面積上的簡化，將隨機位址和隨機選取的電路以洗牌網絡的方式做設計，利用每個邊緣記憶體擁有低相關性洗牌順序的設計，使得此洗牌機制的變數點運算單元可以達到打散資料之間相關性的特性，與先前記憶體相比可以有效降低所需面積，以IEEE標準中的(576,288)的檢查矩陣實驗，此設計可達到與先前邊緣記憶體相近的解碼能力。

    Stochastic decoders provide a low-complexity solution for the decoding of binary Low-Density Parity Check (LDPC) code. However, the assumptions of stochastic computation may be violated during iterative decoding, resulting in the latching problem and an error floor in the performance of the LDPC decoder.
    This thesis proposes a new edge memory approach, designated as shuffle-based edge memory (SEM), for alleviating the latching problem. In the proposed method, the area consumption of the early edge memory (EEM) technique is reduced by replacing the random number generator and selector in EEM with a shuffle network designed to randomly assign each edge a low-correlated pattern. Experimental results obtained for the (576, 288) LDPC code, show that the BER performance of the proposed SEM decoder is comparable with that of the traditional EEM technique.

    Content…... iv List of Tables vi List of Figures vii Chapter 1. Introduction 1 1.1 Digital communication system and Error control code 2 1.2 Motivation 3 1.3 Thesis organization 5 Chapter 2. Background 6 2.1 Low-density parity check code 6 2.1.1 Code Structure and parity-check matrix 6 2.1.2 Encoding of binary LDPC 10 2.1.3 Decoding of binary LDPC 10 2.2 Stochastic computation 14 2.2.1 Stochastic message representation 15 2.2.2 Stochastic computation unit 15 2.3 Stochastic decoding in LDPC 17 2.3.1 Information converter and Random number generator 18 2.3.2 Stochastic check node and variable operator 19 2.3.3 Latching problem 21 2.3.4 Possible solution for latching problem 25 Chapter 3. Different embodiment of variable node operator 30 3.1 Latching problem at different level of input correlation 31 3.2 Shuffle-based edge memory 33 3.2.1 Description of shuffle method 34 3.2.2 Randomness analysis 35 3.3 Comparison of two edge memories 44 3.3.1 Structure 44 3.3.2 Decoding ability of variable node operator 47 3.4 Parameter setting in edge memory 48 3.4.1 Edge memory with noise dependent scaling 48 3.4.2 Initial time of edge memory 49 3.4.3 Length of edge memory 50 Chapter 4. Simulation Results 52 4.1 (576, 288) Parity check matrix chosen from IEEE 802.16e standard 52 4.2 Bit error rate decoding performance 52 Chapter 5. Conclusion and Future Work 56 5.1 Conclusion 56 5.2 Future work 57 References….. 58

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