本論文主要提出一個嵌入式共模雜訊抑制電路架構，其電路主要由被動式架構所組成，其包含有一個共模變壓器和若干電容、電阻元件。文中採用根軌跡理論求取最佳電路參數，以減小共模電流並消除其振盪成分，在最佳電路參數下電磁雜訊也將可有效降低。經由理論分析再配合模擬與實驗結果可進一步證明本文所提出之共模雜訊抑制電路可有效降低傳導電磁雜訊干擾。本文並對緩振電路於雜訊抑制上做相關的分析，配合共模雜訊抑制電路以更有效減少電磁雜訊干擾。

This thesis presents an embedded-type common-mode noise suppressor, which mainly consisting of passive components, such as a common-mode transformer, some capacitors and resisters. Applying the root locus method, the optimum parameter of the circuit is designed to reduce the common-mode current and the ring when the switch device is turn-on or turn-off. So the electromagnetic interference (EMI) noise can be effectively reduced. The experimental results are consistent with the theoretical calculations and prove that the proposed common-mode noise suppressor is valid for reducing EMI noise. We apply both snubber circuit and common-mode noise suppressor to reduce EMI more effectively.

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