耗電量在現今嵌入式處理器設計上是一個重要的考量，相關研究指出指令快取記憶體的耗電量在處理器中佔了很大的比例。以英特爾(Intel) SA-110處理器為例，指令快取記憶體佔整個處理器耗電量的27%。目前許多省電型嵌入式處理器中，指令快取記憶體不再採用傳統RAM (random access memory)-tag設計，而改用高關聯性(highly-associative)、CAM (content addressable memory)-tag、區塊化(banked)的設計來減低耗電量，故以往針對RAM-tag指令快取記憶體所提出的省電機制在高關聯性CAM-tag指令快取記憶體中並不適用。因此本研究藉著way locality的特性，以及增加分支目標緩衝器的欄位，來節省高關聯性CAM-tag指令快取記憶體的耗電量。同時本研究採用了lazy BTB 技術來減少因增加分支目標緩衝器欄位所帶來額外的耗電量。實驗結果顯示，提出的設計在32KB、32-way的CAM-tag指令快取記憶體中至少可減少34% 的耗電量，且節省了50% 查詢分支目標緩衝器所需的耗電量，而無嚴重的效能減損。

Energy consumption is an important design consideration of modern embedded processors. It has been shown that the instruction cache accounts for a significant portion of energy dissipation of the whole processor. For example, the Intel SA-110 low-power microprocessor dissipates 27 percent of total processor power in the instruction cache.
At present, the instruction caches in a lot of low-power embedded processors do not use the traditional RAM-tag design; they employ highly-associative, CAM (content addressable memory)-tag and banked design for reducing energy consumption. So the previously proposed low-power mechanisms for RAM-tag instruction caches are not applicable in the highly-associative CAM-tag structure. In this study, the proposed design reduces the energy consumptions of instruction caches by taking the characteristic of way locality. Additionally, the lazy BTB technique is used to reduce extra BTB energy overhead caused due to the added BTB fields. The experimental results show that the proposed design can reduce the energy consumptions of a 32KB, 32-way instruction cache at least by 34 percent and BTB look-up by 50 percent with negligible performance degradation.

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