此論文提出兩個針對5G行動通訊應用的K頻段LC壓控振盪器(VCO)電路架構，為了資料傳輸的品質，因此需要產生低相位雜訊的LO訊號。兩電路架構的特點皆是採用共模（CM）諧振擴展技術加上 Class-F 操作原理，以達到在頻寬內都能達到抑制閃爍雜訊上轉換，藉由在二次與三次諧波處形成共振，來有效優化脈衝靈敏度函數（ISF）之波形，提升相位雜訊效能。此外，透過設計變壓器本身所具備的共模耦合係數（kCM），可擴展共模共振頻寬，無需手動調整以對準二次諧波，使VCO同時具備優異的相位雜訊表現。
第一個架構為傳統的變壓器諧振腔VCO，主要是利用設計共模耦合係數，來達到振盪頻率範圍內都能維持很好的相位雜訊表現，並且相對目前所提出的類似架構而言，此架構不需佔用額外的晶片面積，此電路以台積電40奈米CMOS技術實現，核心電路面積僅0.05 mm2，並且操作於23.9 至 27.5 GHz的頻率，在 1 MHz 偏移處達成 -104.5 dBc/Hz 的相位雜訊，在0.6 V 供應電壓下功耗僅為 5.4 mW。其 fig-ure-of-merit（FoM）與考慮可調範圍的 FoMT 分別為 184.7 與 187.6 dBc/Hz
而第二個架構的諧振腔則是以交叉耦合變壓器取代傳統變壓器設計，使其消耗功率能夠進一步降低，也增加了可設計的參數以減少電路設計複雜度。與第一個架構同樣使用台積電40奈米技術實現，核心面積僅0.04 mm2，此VCO的振盪頻率操作於19.5到22.7 GHz，在0.5 V 供應電壓下達到1 MHz偏移處有-102.4 dBc/Hz 的相位雜訊表現，功率消耗僅有3.0 mW，量測結果與模擬的落差是由於量測環境尚未完善，其中包含環境雜訊以及地線雜訊可能耦合到振盪器電路之中，導致相位雜訊劣化。若能進一步改善量測環境，相位雜訊的實際表現有望更接近模擬結果，進一步驗證所提出架構的有效性。

This thesis presents two K-band LC voltage-controlled oscillator (VCO) architectures targeting 5G mobile communication applications, where a low-phase-noise local oscillator (LO) is critical for ensuring high-quality data transmission. Both proposed VCOs employ a combination of common-mode (CM) resonance expansion and Class-F operation to suppress flicker noise up-conversion across a wide tuning range. By inducing resonances at the second and third harmonic frequencies, the impulse sensitivity function (ISF) waveform is effectively shaped, thereby enhancing phase noise performance. Furthermore, by leveraging the inherent common-mode coupling coefficient (kCM) of the transformer, the CM resonance bandwidth can be extended without requiring manual tuning of single-ended capacitance to align with the second harmonic, enabling consistent low phase noise across the tuning range.
The first VCO architecture is based on a conventional transformer-based LC tank. By carefully designing the CM coupling coefficient, this structure achieves wideband CM resonance while maintaining a compact layout with no additional chip area compared to prior work. Implemented in TSMC 40-nm CMOS technology, the core occupies only 0.05 mm² and operates from 23.9 GHz to 27.5 GHz. It achieves a phase noise of –104.5 dBc/Hz at 1 MHz offset while consuming only 5.4 mW from a 0.6 V supply. The corresponding fig-ure-of-merit (FoM) and tuning-aware FoMT are 184.7 dBc/Hz and 187.6 dBc/Hz, respec-tively.
The second VCO architecture replaces the conventional transformer with a cross-connected transformer to further reduce power consumption and provide more flexibil-ity in design parameter optimization, thus simplifying circuit implementation. Similar to the first architecture, the circuit is implemented in TSMC 40-nm CMOS technology, with a compact core area of only 0.04 mm². The VCO operates over a frequency range of 19.5–22.7 GHz, achieving a phase noise of –102.4 dBc/Hz at 1-MHz offset under a 0.5-V supply, while consuming only 3.0 mW of power. The discrepancy observed between the measured and simulated results is attributed to limitations in the measurement setup, where environmental noise and ground loop interference may have coupled into the oscillator core. With further refinement of the measurement environment, the phase noise performance is expected to more closely align with simulation, thereby further validating the effectiveness of the proposed architecture.

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