本論文提出10位元每秒500百萬次取樣速率數位類比轉換器。該轉換器以5+5區段式架構搭配電流導向式方式實現，其中5位元的高位元部分為等電流單元，5位元的低位元部分為加權二進制單元。
　　為了達到每秒500百萬次轉換速率，必須以電晶體層級全系統的設計溫度計解碼器以及同步電路。在數位部分，設計具備高速度以及高輸出交越點的門閂電路以降低突波能量。同時，在類比部分採用疊接電流源電晶體以增加輸出阻抗以及改善SNDR與SFDR效能。
　　根據模擬結果，突波能量約0.995 psec-V。以輸入訊號接近250 MHz且取樣頻率為500 MHz的情況下，可得SNDR約為60dB。該DAC採用單一電壓3.3V，功率消耗為70mW。採用適當的電流源電晶體面積以克服製程不匹配所造成的誤差之後。該DAC晶片採用TSMC 0.18μm 1P6M CMOS製程來實現，整體晶片的面積為1.07mm×1.07mm。

　In this paper, a 10-bit 500-MSample/s CMOS digital-to-analog (D/A) converter is presented. It is based on a current steering segmented 5 + 5 architecture that comprises 5MSB’s unary cells and 5LSB’s binary weighted cells in this design.
　The 500-MSample/s conversion rate has been obtained by an, at transistor level, fully custom designed thermometer decoder and synchronization circuit. In the digital part, a high speed, high output crossing-point latch is designed to minimize the glitch energy. Moreover, using cascade current cell in analog part can increase the output impedance and improve the performance of the SNDR and SFDR.
　From the simulation result, the glitch energy is 0.995 psec-V. For a near 250 MHz input signal at 500 MHz sampling rate, the SNDR is about 60dB. The power consumption of this DAC with a single 3.3V supply is 70 mW. Proper area of current source transistor is chosen to overcome mismatch error due to process variation. This DAC chip is fabricated using TSMC 0.18μm-1P6M CMOS process and the die area is 1.07mm×1.07mm.

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