本論文提出應用於24-GHz CMOS及60-GHz CMOS毫米波(MMW)射頻前端接收機的設計K-band之收發開關及V-band收發機(transceiver)之低雜訊放大器(LNA)之設計。
論文分為四個部分，第一部分為介紹K-band及V-band毫米波系統相關背景和應用，以及提出57- 64 GHz MMW與3- 10 GHz MB-OFDM UWB 共存系統的規劃。第二部分為應用於K-band收發開關的電路設計和量測結果，使用製程為TSMC 0.18-µm 1P6M RF CMOS，主要內容包含電路之設計及提出LC-resonate電路技術來提升隔離度及降低插入損耗，操作頻率在21-GHz到27-GHz；操作電壓提供為1.8V(ON)/0V(OFF) ；在TX mode時之插入損耗，也就是訊號從發射端(Port1)傳到天線端(Port3)之插入損耗為4.6dB；發射端(Port1)與接收端 (Port2)之隔離度為33.5dB；P1dB壓縮點為20dBm ；Port1反射損耗為-11.4dB； Port3反射損耗為-11.6dB；在RX mode時之插入損耗，也就是訊號從Port3傳到Port2之插入損耗為4.5dB；Port3與Port1之隔離度為28.3dB；Port1反射損耗為-11.4dB；Port3反射損耗為-12.7dB。
第三部分為應用於V-band毫米波之低雜訊放大器的電路設計和量測結果，使用製程為TSMC 90-nm 1P9M RF CMOS製程。此部份主要探討提升放大器增益的閘極電感增益提升 (gate-inductor gain peaking) 技術。閘極電感增益提升技術對於低功率消耗的條件下提升毫米波低雜訊放大器的增益是一有效的方法。晶片量測結果顯示，操作頻率在52-GHz時，小訊號增益為17.1 dB；雜訊指數為8.2 dB；輸入1-dB增益壓縮點為 -27dBm；輸入之三階交錯點(IIP3)為 -19dBm；供應電壓VDD為1.2 V；整體消耗功率為24mW，第四部分為整體的總結。

The thesis aims to the designs of 24-GHz and 60-GHz CMOS front-end function block of the millimeter wave (MMW) RF transmitter and receiver: switch(T/R switch) is designed for the K-band applications, and the low noise amplifier (LNA) is for the V-band.
The paper is divided into four parts. First, We introduce the related background and applications of millimeter wave systems. Also, we propose a 60-GHz mm-Wave and MB-OFDM UWB co-existence system. The second part of this thesis presents the design and measurement results of a T/R switch. The circuit is implemented by TSMC 0.18- µm 1P6M RF CMOS process. The main focus is on the T/R switch circuit design and the use of an LC-resonant circuit technology to improve the level of isolation and to lower the insertion loss. The supply voltage of T/R switch is 1.8 V. The measurement data show that the T/R switch in the TX mode, the signal from transmit Port (Port1) to antenna Port (Port3) is 4.6dB, The isolation from Port1 to receive point Port2 is 33.5dB, and the input 1-dB compression point (P1dB) is 20dBm, the return loss of Port3 is -11.6dB, and that of Port2 is -12.7dB. When the T/R switch in the RX mode, the signal from Port3 to Port2 is 4.5 dB; the isolation from Port3 to Port1 is 28.3 dB; the input 1-dB compression point (P1dB) is 20dBm; the return loss of Port1 is -11.4dB; and the Port3 is -12.7dB.
The third part of this thesis presents the design and measurement results of an MMW LNA. The LNA was fabricated in TSMC 90-nm 1P9M RF CMOS process. The main focus is on the gate-inductor gain peaking technique to increase LNA’s gain. The gate-inductor gain peaking technology is an effective methodology to achieve the high gain performance with low power consumption. The measurement data show that the LNA can achieve a peak gain of 17.1 dB and a noise figure (NF) of 8.2 dB at 52-Hz, an input 1-dB compression point (P1dB) of -27dBm at 52-GHz, and an input third-order intercept point (IIP3) of -19dBm. Also, the LNA consumes only 24mW at a supply voltage of 1.2 V. The fourth part is the conclusion.

[1] H.S. Momose, E. Morifuji, T. Yoshitomi, T. Ohguro, M. Saito and H. Iwai, “Cutoff frequency and propagation delay time of 1.5-nm gate oxide CMOS,”IEEE Trans. On Electron Devices,vol.48, no.6,pp.1165-1174,June 2001.
[2] E. Grass, “Implementation Aspects of Gbit/s Communication System for 60 -GHz Band,” Wireless World Research Forum.
[3] C.H. Doan, S Emami, D.A. Sobel, A.M. Niknejad and R.W. Brodersen, “Design considerations for 60-GHz CMOS radios,” IEEE Communications Magazine, Vol. 42, No. 12, pp.132-140, Dec.2004
[4] H. Xu, K.O. Kenneth, “A 31.3-dBm Bulk CMOS T/R Switch Using Stacked Transistors With Sub-Design-Rule Channel Length in Floated p-Wells,” IEEE Journal of Solid-State Circuits, Vol. 42, No. 11, pp. 2528–2534, Oct. 2007
[5] M. Ahn, C.-H. Lee Byung, Sung Kim and L.J., “A High-Power CMOS Switch Using A Novel Adaptive Voltage Swing Distribution Method in Multistack FETs” IEEE Transactions on Microwave Theory and Techniques, Vol.56, No.4, pp.849-858, April 2008.
[6] A. A. Kidwai, C.-T. Fu and J.C. Jensen , “A Fully Integrated Ultra-Low Insertion Loss T/R Switch for 802.11b/g/n Application in 90-nm CMOS Process, ” IEEE Journal of Solid-State Circuits, Vol. 44, No. 5, pp. 1352–1360, May. 2009
[7] S.-F. Chao, H. Wang, C.-Y. Su and J. G. J. Chern, ” A 50 to 94-GHz CMOS SPDT Switch Using Traveling-Wave Concept,” IEEE Microwave and Wireless Components Letters, pp. 130–132,Vol.17 , No.2 , Feb 2007.
[8] X. J. Li and Y. P. Zhang, “An overview of recent advances in CMOS T/R switch designs,” in IEEE Asia-Pacific Microwave Conference , Jan. 2009 ,pp. 1741–1750.
[9] Z. Li and, K. O. Kenneth , “15-GHz fully integrated nMOS switches in a 0.13-μm CMOS process” IEEE Journal of Solid-State Circuits, Vol. 40, No. 11, pp. 2323–2328, Jan. 2005.
[10] Y. Jin and C. Nguyen, “Ultra-Compact High-Linearity High-Power Fully Integrated DC–20-GHz 0.18-umCMOS T/R Switch,” IEEE Transactions Microwave Theory and Techniques, Vol. 55, No. 1, pp. 30-36, Jan. 2007.
[11] Q. Li and Y.P. Zhang, “CMOS T/R Switch Design: Towards Ultra-Wideband and Higher Frequency, ” IEEE Journal of Solid-State Circuits, Vol. 42, No. 3, pp. 563–570,Mar. 2007.
[12] C.-Y. Ou, C.-Y. Hsu, H.-R. Lin and, H.-R. Chuang, “A High-Isolation High-Linearity 24-GHz CMOS T/R Switch in the 0.18-um CMOS Process,” in European Microwave Integrated Circuits Conference ,Oct.2009, pp.250-253.
[13] P. Park, D. H. , Shin and C.P. Yue, “High-Linearity CMOS T/R Switch Design Above 20 GHz Using Asymmetrical Topology and AC-Floating Bias,”In IEEE Radio Frequency Integrated Circuit Symposium Digest,April, pp. 948–956,2009.
[14] T. P. Wang and H. Wang, “A broadband 42–63 GHz Amplifier Using 0.13 μm CMOS Technology,” In IEEE MTT-S International Microwave Symposium Digest, pp. 1779–1782, Jun. 2007.
[15] C. H. Doan, S. Emami, A. M. Niknejad, and R. W. Brodersen, “Millimeter-Wave CMOS Design,” IEEE Journal of Solid-State Circuits, Vol. 40, No. 1, pp. 144–155, Jan. 2005.
[16] C.-M. Lo, C.-S. Lin, and H. Wang, “A Miniature V band 3-stage Cascade LNA in 0.13-μm CMOS,” in IEEE International Solid-State Circuits Conf. Digest Techniques Paper, Feb. 2006 s, pp. 402–403.
[17] Y. H. Yu, Y. S. Yang and Y. J. E. Chen, “A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement,” IEEE Journal of Solid-State Circuits, Vol. 45, No. 3, pp. 502-508, Jan. 2010.
[18] C. Inui, I.C.H. Lai and M. Fujishima, “60GHz CMOS Current-Reuse Cascade Amplifier ,” in IEEE Asia-Pacific Microwave Conference, June. 2008, pp. 1–4.
[19] E. Winberg, J. Askne, and G. Skoog, “A Continuously Tuned 53-59 GHz Radiometer for Measurement of Atmospheric Temperature Profiles,” in 14th European Microwave Conference, 1984, pp.243-247.
[20] F. Alimenti, D. Zito, A. Boni, M. Borgarino,A. Fonte, A.Carboni, S. Leone, M. Pifferi, L.Roselli, B. Neri and R. Menozzi “System-on-chip Microwave Radiometer for Thermal Remote Sensing and Its Application to the Forest Fire Detection,” in 15th IEEE International Conference, pp.1265-1268, 2008.
[21] T. Mo, “A Study of the Microwave Sounding Unit on the NOAA-12 Satellite,” IEEE Transactions Geoscience and Remote Sensing, Vol. 33, No. 5, pp.1141-1152, Sep. 1995.
[22] A. Sayag, S. Levin, D. Regev, D. Zfira, S. Shapira, D. Goren and D.Ritter “A 25-GHz 3.3 dB NF Low Noise Amplifier Based Upon Slow Wave Transmission Lines and the 0.18-μm CMOS Technology,” IEEE Radio Frequency Integrated Circuit Symposium Digest, pp. 373–376, Jun. 2008.
[23] S. Pellerano, Y. Palaskas and K. Soumyanath, “A 64 GHz 6.5 dB NF 15.5 dB Gain LNA in 90 nm CMOS,” in Eur. Solid-State Circuit Conf., Sep. 2007, pp. 352–355.
[24] C. Weyers, P. Mayr, J. W. Kunze and U. Langmann, “A 22.3 dB Voltage Gain 6.1 dB NF 60-GHz LNA in 65 nm CMOS With Differential Output,” in IEEE International Solid-State Circuits Conf., Feb. 2008, pp. 192-193.
[25] B.-J. Huang, C.-H. Wang, C.-C. Chen, M.-F. Lei, P.-C. Huang, K.-Y. Lin and H. Wang “Design and Analysis for a 60 GHz Low-Noise Amplifier With RF ESD Protection,” IEEE Transactions Microwave Theory and Techniques, Vol. 57, No. 2, pp. 298-305, Feb. 2009.
[26] B. Razavi, “A 60-GHz CMOS Receiver Front-End,” IEEE Journal of Solid-State Circuits, Vol.41, No.1, pp.17-22, Jan. 2006.
[27] D. Huang, R. Wong, Q. Gu, N.-Y. Wang, T. W. Ku, C. Chien and M.-C. F.Chang, “A 60 GHz CMOS Differential Receiver Front-End Using On-Chip Transformer for 1.2 Volt Operation with Enhanced Gain and Linearity,” in Symp. VLSI Circuits, p.p.144-145 2006.
[28] Y. Sun, F. Herzel, L. Wang, J. Borngraber, W. Winkler, and R. Kraemer, “An Integrated 60 GHz Receiver Front-End in SiGe BiCMOS,” IEEE Silicon Monolithic Integrated Circuits in RF Systems Digest, pp.298-305,Feb. 2006.
[29] B. Razavi, “A 60-GHz CMOS Receiver Front-End,” IEEE Journal of Solid-State Circuits, Vol.41, No.1, pp.17-22, Jan. 2006.
[30] S. Emami, C. H. Doan, A. M. Niknejad, and R. W. Brodersen, “A Highly Integrated 60GHz CMOS Front-End Receiver,” in IEEE International Solid-State Circuits Conference, Feb. 2007, pp.190-191.
[31] Y.-J. E. Chen, K.-H. Wang, T.-N. Luo, and S.-Y. Bai, D. Heo, “Investigation of CMOS Technology for 60-GHz Applications,” in IEEE Southeast Conference., April. 2005, pp.92-95.
[32] C.-C. Huang, H.-C. Kuo, T.-H. Huang and H.-R. Chuang, “Investigation of CMOS Technology for 60-GHz Applications, ”IEEE Microwave and Wireless Components Letters, pp. 104–126, Vol.21 , No.2 , Feb 2011.